Patent classifications
H04Q2213/31
OPTICAL SWITCH WITH ALL-OPTICAL MEMORY BUFFER
Consistent with some disclosed embodiments, an optical switch includes: a scheduler; and a buffer for buffering an optical packet including, arranged in a circuit, a clock generator for generating a clock signal, an optical unbalanced Mach Zehnder Interferometer (MZI) and a fiber delay line (FDL) having an FDL length, wherein the optical packet has an optical packet signal, wherein the scheduler is configured to insert the optical packet into the buffer and to determine a number of circulations of the optical packet through the circuit, wherein the MZI modulates the clock signal based on the optical packet signal to create a reshaped optical packet after each circulation of the optical packet through the circuit, and wherein the FDL introduces a delay in the optical packet proportional to the FDL length.
Optical switch with all-optical memory buffer
Consistent with some disclosed embodiments, an optical switch includes: a scheduler; and a buffer for buffering an optical packet including, arranged in a circuit, a clock generator for generating a clock signal, an optical unbalanced Mach Zehnder Interferometer (MZI) and a fiber delay line (FDL) having an FDL length, wherein the optical packet has an optical packet signal, wherein the scheduler is configured to insert the optical packet into the buffer and to determine a number of circulations of the optical packet through the circuit, wherein the MZI modulates the clock signal based on the optical packet signal to create a reshaped optical packet after each circulation of the optical packet through the circuit, and wherein the FDL introduces a delay in the optical packet proportional to the FDL length.
OPTICAL SWITCH WITH ALL-OPTICAL MEMORY BUFFER
Consistent with some disclosed embodiments, an optical switch includes: a scheduler; and a buffer for buffering an optical packet including, arranged in a circuit, a clock generator for generating a clock signal, an optical unbalanced Mach Zehnder Interferometer (MZI) and a fiber delay line (FDL) having an FDL length, wherein the optical packet has an optical packet signal, wherein the scheduler is configured to insert the optical packet into the buffer and to determine a number of circulations of the optical packet through the circuit, wherein the MZI modulates the clock signal based on the optical packet signal to create a reshaped optical packet after each circulation of the optical packet through the circuit, and wherein the FDL introduces a delay in the optical packet proportional to the FDL length.
Optical switch with all-optical memory buffer
Consistent with some disclosed embodiments, an optical switch includes: a scheduler; and a buffer for buffering an optical packet including, arranged in a circuit, a clock generator for generating a clock signal, an optical unbalanced Mach Zehnder Interferometer (MZI) and a fiber delay line (FDL) having an FDL length, wherein the optical packet has an optical packet signal, wherein the scheduler is configured to insert the optical packet into the buffer and to determine a number of circulations of the optical packet through the circuit, wherein the MZI modulates the clock signal based on the optical packet signal to create a reshaped optical packet after each circulation of the optical packet through the circuit, and wherein the FDL introduces a delay in the optical packet proportional to the FDL length.
OPTICAL SWITCH WITH ALL-OPTICAL MEMORY BUFFER
Consistent with some disclosed embodiments, an optical switch includes: a scheduler; and a buffer for buffering an optical packet including, arranged in a circuit, a clock generator for generating a clock signal, an optical unbalanced Mach Zehnder Interferometer (MZI) and a fiber delay line (FDL) having an FDL length, wherein the optical packet has an optical packet signal, wherein the scheduler is configured to insert the optical packet into the buffer and to determine a number of circulations of the optical packet through the circuit, wherein the MZI modulates the clock signal based on the optical packet signal to create a reshaped optical packet after each circulation of the optical packet through the circuit, and wherein the FDL introduces a delay in the optical packet proportional to the FDL length.