A ceramic carrier substrate for an electrical/electronic circuit. The substrate includes ceramic layers arranged one above the other in an interconnected structure and conductor tracks arranged on and/or in individual ceramic layers and connected to one another as the conductor structure for the electrical/electronic circuit. The interconnected structure is formed by a firing operation. A first conductor substructure is formed in a first interconnected structure subassembly which comprises at least one of the ceramic layers, and a second conductor substructure is formed in a second interconnected structure subassembly which is directly adjacent to the first interconnected structure subassembly and comprises at least one of the ceramic layers. The second conductor substructure substantially consists of high-current conductor tracks and is configured to contact a power circuit. The first conductor substructure substantially consists of signal conductor tracks and is configured to contact a drive circuit for the power circuit.

To improve a TCT characteristic of a circuit substrate. The circuit substrate comprises a ceramic substrate including a first and second surfaces, and first and second metal plates respectively bonded to the first and second surfaces via first and second bonding layers. A three-point bending strength of the ceramic substrate is 500 MPa or more. At least one of L1/H1 of a first protruding portion of the first bonding layer and L2/H2 of a second protruding portion of the second bonding layer is 0.5 or more and 3.0 or less. At least one of an average value of first Vickers hardnesses of 10 places of the first protruding portion and an average value of second Vickers hardnesses of 10 places of the second protruding portion is 250 or less.

An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

A system of circuit card components each include through-holes for soldering having recessed copper layers for thermal insulation. Thermal insulation prevents heat conduction away from flowing solder, allowing the solder to flow freely through the through-hole. Even high-temperature, lead-free solders may maintain the necessary temperature to flow. Different circuit layers include specialized features based on distance from a top or bottom surface. Vias surrounding the through-hole maintain the necessary cross-sectional area for electrical connectivity.

The present disclosure relates to systems and methods using thermal vias to increase the current-carrying capacity of conductive traces on a multilayered printed circuit board (PCB). In various embodiments, parameters associated with vias may be selected to control various electrical and thermal properties of the conductive trace. Such parameters include the via diameter, a plating thickness, a number of vias, a placement of the vias, an amount of conductive material to be added or removed from the conductive trace, a change in the resistance of the conductive trace, a change in a fusing measurement of the conductive trace, and the like.

A flexible printed circuit board includes a base film having an insulating property, and multiple interconnects laminated to at least one surface side of the base film. The multiple interconnects include a first interconnect and a second interconnect in a same plane. An average thickness of the second interconnect is greater than an average thickness of the first interconnect. A ratio of the average thickness of the second interconnect to the average thickness of the first interconnect is greater than or equal to 1.5 and less than or equal to 50.

A wiring circuit board includes an insulating layer, a pair of wiring layers, an insulating layer, and a wiring layer. The pair of wiring layers are disposed on the insulating layer and extend side by side apart from each other. The insulating layer is disposed on the insulating layer so as to cover the pair of wiring layers. The wiring layer is disposed on the insulating layer and extends along the pair of wiring layers, while facing to the pair of wiring layers in a thickness direction of the wiring layer. The wiring layer has a ridge portion. The ridge portion protrudes into the insulating layer toward a region between the wiring layers and extends along the region.

An integrated power control assembly mounted on an axial end of a three-phase motor includes a substrate, two input busbars each of positive and negative polarities alternatively spaced apart on the substrate, a plurality of sets of paired devices, and three output busbars corresponding to the three phases of the motor, wherein a set of paired devices includes a switching semiconductor and a diode. An inner input busbar has edges adjacent to an inner input busbar of opposite polarity and an outer input busbar of opposite polarity and configured to have at least twice as many devices as the outer input busbars. One or more sets of paired devices are disposed axially on outer input busbars and on inner input busbars along the edges. An individual output busbar is disposed over and electrically coupled to one or more sets of paired devices disposed on adjacent input busbars of opposite polarity.

A single circuit board assembly for forming a vehicle-motor interface, the single circuit board assembly includes a first side of a board with logic modules located thereon. The single circuit board assembly also includes a second side of the board with power modules located thereon. The board comprises a plurality of layers, the plurality of layers having at least one through via and at least one buried via defined therein, wherein the at least one through via extends through all of the plurality of layers, the at least one buried via extending through less than all of the plurality of layers.

An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.