A ceramic carrier substrate for an electrical/electronic circuit. The substrate includes ceramic layers arranged one above the other in an interconnected structure and conductor tracks arranged on and/or in individual ceramic layers and connected to one another as the conductor structure for the electrical/electronic circuit. The interconnected structure is formed by a firing operation. A first conductor substructure is formed in a first interconnected structure subassembly which comprises at least one of the ceramic layers, and a second conductor substructure is formed in a second interconnected structure subassembly which is directly adjacent to the first interconnected structure subassembly and comprises at least one of the ceramic layers. The second conductor substructure substantially consists of high-current conductor tracks and is configured to contact a power circuit. The first conductor substructure substantially consists of signal conductor tracks and is configured to contact a drive circuit for the power circuit.

A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, at least one second build-up circuit layer, at least one conductive through hole, and a fine redistribution layer (RDL). The embedded block is fixed in a through cavity of the dielectric substrate. The electronic component is disposed in an opening of the embedded block. The first build-up circuit layer is disposed on a top surface of the dielectric substrate and electrically connected with the electronic component. The second build-up circuit layer is disposed on a bottom surface of the dielectric substrate and covers the embedded block. The conductive through hole is disposed in a via of the embedded block and electrically connects the first and the second build-up circuit layers. The fine RDL is disposed on and electrically connected to the first build-up circuit layer.

A printed circuit board may include a substrate body portion, conductive patterns on a top surface of the substrate body portion, and a photosensitive insulating layer on the top surface of the substrate body portion and including an opening exposing at least one of the conductive patterns. The photosensitive insulating layer includes first to third sub-layers stacked sequentially. The first sub-layer includes an amine compound or an amide compound A refractive index of the second sub-layer is lower than a refractive index of the third sub-layer. A photosensitizer content of the second sub-layer is higher than a photosensitizer content of the third sub-layer.

Prepregs having a UV curable resin layer located adjacent to a first thermally curable resin layer or sandwiched between first and second thermally curable resin layers wherein the UV curable resin layer is uncured or partially cured as well as methods for preparing laminates using the prepregs wherein the laminate includes at least one UV curable resin encapsulated electrical component.

Described herein are dielectric polymer films and printed circuit boards, such as multilayer and high-density interconnect printed circuit board comprising at least one dielectric polymer film.

A multi-layer and method of making the same are provided. The multi-layer, such as a sensor, can include a high strength glass overlay and a lamination layer on a substrate layer. The overlay can be less than 250 micrometers thick and have at least one tempered surface incorporating a surface compression layer of at least 5 micrometers deep and a surface compressive stress of at least 200 MPa. The overlay can exhibit a puncture factor of at least 3000 N/μm.sup.2 at B10 (10.sup.th percentile of the probability distribution of failure) in a multi-layer structure, an apparent thickness of less than 0.014 mm, and a pencil hardness greater than 6H. The method can include ion-exchange tempering at least one major surface of a glass sheet, light etching the major surface to remove flaws and laminating the glass sheet on the tempered and lightly etched major surface to a substrate layer.

The present invention relates to a resin film for a flexible printed circuit board consisting of a resin composition containing: a long-chain alkyl bismaleimide resin having a main chain containing an alkylene chain having 10 or more carbon atoms and a side chain containing an alkyl group bonded to the alkylene chain; and a curing agent having two or more functional groups reacting with the long-chain alkyl bismaleimide resin.

[Problem] To achieve a wiring board capable of suppressing the difference in the amount of delay between two signal wirings constituting differential signal wirings, while securing flexibility in design.

[Solution] A wiring board is configured to include a first insulating layer 1, a first signal wiring 2 and a second signal wiring 3. The first insulating layer 1 includes fibers 4 having the long axis in a first direction and aligned approximately parallel to each other at a first interval and an insulating material 5 filling gaps between the fibers 4 of the first direction. The first signal wiring 2 is formed approximately parallel to the first direction on the first insulating layer 1. The second signal wiring 3 is formed parallel to the first signal wiring 2 such that the interval between the first and second signal wirings 2 and 3 be approximately an integral multiple of the first interval, and the second signal wiring 3 transmits a differential signal of a signal transmitted on the first signal wiring 2.

Disclosed is an adhesive film for circuit connection. This adhesive film for circuit connection includes a first adhesive layer containing conductive particles, a cured product of a photocurable resin component, and a first thermosetting resin component, and a second adhesive layer provided on the first adhesive layer and containing a second thermosetting resin component. A thickness of the first adhesive layer is 5 μm or less.

A method for contacting and rewiring an electronic component embedded in a PCB in the following manner is disclosed. A first permanent resist layer is applied to one contact side of the PCB. The first permanent resist layer is structured to produce exposures in the area of contacts of the electronic component. A second permanent resist layer is applied onto the structured first permanent resist layer. The second permanent resist layer is structured to expose the exposures in the area of the contacts and to produce exposures in line with the desired conductor tracks. The exposures are chemically coated with copper the copper is electric-plated to the exposures. Excess copper in the areas between the exposures is removed.