The present disclosure generally relates to a shielded three-layer patterned ground structure in a PCB. The PCB may be disposed in a hard disk drive. To reduce costs, PCBs are being made with only four total layers separated by dielectric material. Conductive traces in PCBs can have the problem of common mode current flowing through the traces and thus increasing the magnitude of EMI noise. By providing a shielded three-layer patterned ground structure, not only is the cost reduced, but so is the common mode current and the magnitude of EMI noise, all without any negative impact to the differential signal.

Provided is a method for masking a sensitive signal by injecting noise into planes of a printed circuit board (PCB). The method comprises detecting, by a secondary integrated circuit (IC), a noise signal on a shared plane of a PCB that includes the secondary IC. The noise signal may be analyzed to determine the characteristics of the noise signal. A masking signal may be generated based on the characteristics. The masking signal may then be injected onto the shared plane.

Certain aspects of the present disclosure relate to methods and apparatus for allocating resources for the transmission of scheduling requests based on UE traffic profiles. In one embodiment, a base station determines, for one or more user equipments (UEs), a type of traffic to be exchanged between the one or more UEs and the base station. The base station allocates resources for the one or more UEs to use for sending a scheduling request based, at least in part, on the type of traffic associated with each of the one or more UEs. The base station signals an indication of the allocated resources to each of the one or more UEs.

A method and apparatus for inputting a plurality of different circuit schematics designed with printed circuit board (PCB) mountable components; extracting circuit topologies for said plurality of different circuit schematics; transforming said extracted circuit topologies to a fixed number of connection points; and generating a configurable circuit PCB physical layout pattern having said fixed number of connection points such that said PCB mountable components when positioned on one or more of said fixed number of connection points can implement any circuit represented by said plurality of different circuit schematics.

A power converter module includes a multilayer printed circuit board, a switching device, a capacitor device, a first via, a second via, a third via and a fourth via. The multilayer printed circuit board has a first surface and a second surface and includes a plurality of copper layers including a plurality of positive copper layers and negative copper layers. The plurality of positive copper layers and the negative copper layers are disposed in staggered arrangement. The switching device is disposed on the first surface and includes a switching positive terminal and a switching negative terminal. The capacitor device is disposed on the first surface and includes a capacitor positive terminal and a capacitor negative terminal, and the capacitor device forms a capacitor area. The projections of the adjacent positive and negative copper layers and the capacitor area on the first surface at least partially overlap with each other.

Apparatus and methods are provided for providing provide high-speed traces in inner layers of semiconductor packages or PCBs. In an exemplary embodiment, there is provided an circuit assembly that may comprise a first ground reference plane, a second ground reference plane and a dielectric layer between the first ground reference plane and the second ground reference plane. The dielectric layer may comprise a pair of traces embedded therein and the first ground reference plane may have an opening corresponding to the pair of traces. The opening may have a width equal to or larger than a width of the pair of traces, which may be equal to widths of respective traces of the pair of traces and a gap between the pair of traces.

An embodiment provides a circuit board including: a terminal part including a plurality of first terminals, a body part spaced apart from the terminal part and including a plurality of second terminals, and a wire part between the terminal part and the body part, wherein the wire part includes a power wire and a ground wire connecting the plurality of first terminals and the plurality of second terminals, and the ground wire is disposed more outward than the power wire, within the wire part.

Embodiments described herein are directed to methods and apparatus for power distribution. The apparatus can include a power distribution network for a plurality of integrated circuits (IC). According to embodiments, the power distribution network includes a plurality of overlapping power/ground (PG) plane segments and one or more non-overlapping PG (no-PG) plane segments. Each overlapping-PG plane segment is separated from another overlapping-PG plane segment by at least one no-PG plane segment. The no-PG plane segments can include at least one of a multilayered power (P) plane segment with no ground reference of any PG plane and a multilayered ground (G) plane segment with no power reference of any PG plane.

A disclosed apparatus may be a circuit board that includes (1) a first unique sublaminate that includes a plurality of ground layers and a plurality of signal layers, (2) a second unique sublaminate that includes a plurality of power layers and another plurality of signal layers, and (3) a symmetry axis that bisects the circuit board between the first unique sublaminate and the second unique sublaminate, wherein the first unique sublaminate and the second unique sublaminate are distinct from one another. Various other apparatuses, systems, and methods are also disclosed.

An apparatus includes a substrate, a switching device, a capacitor device, a first via, a second via, a third via and a fourth via. The substrate has a first surface and a second surface and includes a plurality of copper layers including M positive copper layers and N negative copper layers. The M positive copper layers and the N negative copper layers are alternated. The switching device is disposed on the first surface and includes a switching positive terminal and a switching negative terminal. The capacitor device is disposed on the first surface and includes a capacitor positive terminal and a capacitor negative terminal, and the capacitor device forms a capacitor area. The projections of the adjacent positive and negative copper layers and the capacitor area on the first surface at least partially overlap with each other.