A printed wiring board includes an insulation layer, conductive pads formed on the insulation layer and positioned to connect an electronic component, and a conductive wiring pattern including first and second conductive patterns and formed on the insulation layer such that the conductive wiring pattern is extending between the conductive pads. The first pattern includes first wiring lines, the second pattern includes second wiring lines, the first and second conductive patterns are formed such that the first wiring lines and the second wiring lines are alternately arrayed on the insulation layer, each of the first wiring lines includes a first metal layer formed on an interface with the insulation layer, each of the second wiring lines includes a second metal layer formed on an interface with the insulation layer, and the first metal layer includes a metal material which is different from a metal material forming the second metal layer.

Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

A semiconductor package includes a package substrate including a first voltage substrate wire, an interposer substrate provided on the package substrate and including a first voltage interposer wire, a first semiconductor chip mounted on a top surface of the interposer substrate, and a voltage control chip provided on the top surface of the interposer substrate and laterally spaced apart from the first semiconductor chip, wherein the first semiconductor chip is electrically connected to the voltage control chip through the first voltage substrate wire, and wherein the first semiconductor chip is electrically connected to the voltage control chip through the first voltage interposer wire.