Embodiments presented in this disclosure generally relate to techniques for interconnecting integrated circuits. More specifically, embodiments disclosed herein provide a back mounted interposer (BMI) to facilitate interconnecting of integrated circuits. One example apparatus includes an integrated circuit, an interposer, and a circuit board, at least a portion of the circuit board being disposed between the integrated circuit and the interposer, where the circuit board is configured to provide electrical connection between the interposer and the integrated circuit via connection elements on a first surface of the interposer. The apparatus also includes an interface on a second surface of the interposer, the interface being configured to provide signals from the integrated circuit to an electrical component.

A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.

An electrical connectors with electrodeposited terminals that are grown in place by electroplating cavities formed in a series of resist layers. The resist layers are subsequently stripped away. The resulting terminal shape is defined by the shape of the cavity created in the resist layers. Complex terminal shapes are possible. The present conductive terminals are particularly useful for electrical interconnects and semiconductor packaging substrates.

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include at least two integrated circuit dies that communicate using an embedded multi-die interconnect bridge (EMIB) in a substrate of the multi-chip package. The EMIB may receive power at contact pads formed at a back side of the EMIB that are coupled to a back side conductor on which the EMIB is mounted. The back side conductor may be separated into multiple regions that are electrically isolated from one another and that each receive a different power supply voltage signal or data signal from a printed circuit board. These power supply voltage signals and data signals may be provided to the two integrated circuit dies through internal microvias or through-silicon vias formed in the EMIB.

Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

An electronic device and methods for fabricating the same are disclosed herein that utilize a dam formed on a printed circuit board (PCB) that is positioned to substantially prevent edge bond material, utilized to secure a chip package to the PCB, from interfacing with the solder balls transmitting signals between the PCB and chip package.

Systems, methods, and devices for a ball grid array with non-linear conductive routing are described herein. Such a ball grid array may include a plurality of solder balls that are electrically coupled by a non-linear conductive routing. The non-linear conductive routing may include a plurality of routing sections where each of the plurality of routing sections is disposed at an angle to adjacent routing sections.

A printed circuit board includes: a substrate structure having a first surface including a chip mounting region on which a semiconductor chip is mounted and a second surface opposite to the first surface, the second surface having a rectangular shape having first to fourth edges and first to fourth corners formed by the first to fourth edges, and pad patterns on the second surface of the substrate structure, wherein the second surface includes a first region including a region corresponding to the chip mounting region and in contact with the first to fourth edges, respectively, and second regions adjacent to the first to fourth corners, respectively and spaced apart from each other by the first region, wherein the pad patterns include first pad patterns in the first region and surface-treated with a nickel/gold (Ni/Au) layer, and second pad patterns in the second regions and surface-treated with an organic solderability preservative.