Provided is a carrier-attached metal foil which can suppress the number of foreign matter particles on the surface of a metal layer to enhance circuit formability, and can keep stable releasability even after heating at a high temperature of 240° C. or higher (for example, 260° C.) for a long period of time. The carrier-attached metal foil includes a carrier, a release functional layer provided on the carrier, the release functional layer including a metal oxynitride, and a metal layer provided on the release functional layer.

A method for manufacturing a combined wiring board includes preparing multiple wiring boards, preparing a metal frame having opening portions which accommodate the boards, respectively, positioning the boards in the opening portions of the frame, respectively, and forming multiple crimped portions in the frame by plastic deformation such that the sidewalls of the boards bond to sidewalls of the opening portions in the frame. The preparing of the boards includes forming the sidewalls of the boards such that when the boards are positioned in the opening portions of the frame, the sidewalls of the boards form wide-space portions and narrow-space portions with respect to the sidewalls of the opening portions in the frame, and the forming of the crimped portions includes generating the deformation such that the sidewalls of the opening portions in the frame abut the narrow-space portions of the boards before the wide-space portions of the boards.

Provided is a copper foil provided with a carrier in which the laser hole-opening properties of the ultrathin copper layer are good and which is suitable for producing a high-density integrated circuit substrate. A copper foil provided with a carrier having, in order, a carrier, an intermediate layer, and an ultrathin copper layer, wherein the specular gloss at 60° in an MD direction of the intermediate layer side surface of the ultrathin copper layer is 140 or less.

A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

A process for forming a graphene circuit pattern on an object is described. A graphene layer is grown on a metal foil. A bonding layer is formed on a protective film and a surface of the bonding layer is roughened. The graphene layer is transferred onto the roughened surface of the bonding layer. The protective film is removed and the bonding layer is laminated to a first core dielectric substrate. The metal foil is etched away. Thereafter the graphene layer is etched using oxygen plasma etching to form graphene circuits on the first core dielectric substrate. The first core dielectric substrate having graphene circuits thereon is bonded together with a second core dielectric substrate wherein the graphene circuits are on a side facing the second core dielectric substrate wherein an air gap is left therebetween.

Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Disclosed is a structure of a flexible circuit board combined with a carrier board. The carrier board includes a thick copper layer, a thin copper layer, and a release layer formed between the thick copper layer and the thin copper layer. The flexible circuit substrate and the carrier board are bonded together by an adhesive layer. In a subsequent process, the release layer, together with the thick copper layer, is peeled from a top surface of the thin copper layer and the thin copper layer is preserved by being bonded by the adhesive layer to the flexible circuit substrate.

One embodiment of the present disclosure provides a method for producing a substrate formed with a copper thin layer. The method includes providing a carrier, forming a separation-inducing layer on the surface of the carrier, forming a copper thin layer on the separation-inducing layer, and bonding a core to the copper thin layer.