Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.

There is provided a method for manufacturing a printed wiring board that effectively suppresses pattern failure and is also excellent in fine circuit forming properties. This method includes: providing an insulating substrate including a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 μm thick having a surface having an arithmetic mean waviness Wa of 0.10 μm or more and 0.25 μm or less as measured in accordance with JIS B0601-2001 and a kurtosis Sku of 2.0 or more and 3.5 or less as measured in accordance with ISO 25178; laminating a photoresist on the surface of the electroless plating layer; performing exposure and development to form a resist pattern; applying electroplating to the electroless plating layer; stripping the resist pattern; and etching away an unnecessary portion of the electroless plating layer to form a wiring pattern.

There is provided a method for manufacturing a printed wiring board that effectively suppresses pattern failure and is also excellent in fine circuit forming properties. This method includes: providing an insulating substrate including a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 μm thick having a surface having an arithmetic mean waviness Wa of 0.10 μm or more and 0.25 μm or less and a valley portion void volume Vvv of 0.010 μm.sup.3/μm.sup.2 or more and 0.028 μm.sup.3/μm.sup.2 or less; laminating a photoresist on the surface of the electroless plating layer; performing exposure and development to form a resist pattern; applying electroplating to the electroless plating layer; stripping the resist pattern; and etching away an unnecessary portion of the electroless plating layer to form a wiring pattern.

A stacking structure is applicable to manufacturing a circuit board. The stacking structure includes a transferring layer and a dielectric layer disposed on the transferring layer. The transferring layer includes a substrate and a thin film disposed on the substrate and having a plurality of recess structures thereon. The recess structures are connected as a single piece and bottom portions and top portions of the recess structures are configured to arrange in a staggered manner to form a multi-dimensional arrangement. At least a portion of the dielectric layer being is located in the recess structures, such that the dielectric layer is at least embedded with the recess structures.

The present inventive concept relates to an unfoldable layered connection comprising: a substrate; a node of connector material arranged to contact the substrate; a first extension comprising a core of connector material arranged to be in contact with the node, and flexible material arranged to at least partially enclose the core; a second extension comprising a core of connector material arranged to be in contact with the first extension via a second node of connector material, wherein the first extension is configured to be hingedly connected to the node, thereby allowing unfolding of the first extension along a z-axis being perpendicular to an extension plane of a major surface of the substrate; and wherein the second extension is hingedly connected to the second node, thereby allowing unfolding of the second extension along the z-axis, and wherein the second node is moveable along the z-axis via unfolding of the first extension.

The present inventive concept relates to a foldable layered connection comprising: a substrate having a first major surface and an opposing second major surface; a node of connector material arranged to contact the substrate via the first major surface; a released extension comprising a core of connector material arranged to be in communicative contact with the node of connector material, and flexible material arranged to at least partially enclose the core; wherein the released extension is configured to be hingedly connected to the node and to fold towards the second major surface, and wherein a portion of the core of connector material is exposed, forming a contact of connector material, wherein the contact is electrically isolated from the second major surface and arranged such that it is facing away from the second major surface when the released extension is folded towards the second major surface.

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject mater further discloses methods of electrolytic plating by controlling surface area of an anode.

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject mater further discloses methods of electrolytic plating by controlling surface area of an anode.

A stacking structure is applicable to manufacturing a circuit board. The stacking structure includes a transferring layer and a dielectric layer disposed on the transferring layer. The transferring layer includes a substrate and a thin film disposed on the substrate and having a plurality of recess structures thereon. The recess structures are connected as a single piece and bottom portions and top portions of the recess structures are configured to arrange in a staggered manner to form a multi-dimensional arrangement. At least a portion of the dielectric layer being is located in the recess structures, such that the dielectric layer is at least embedded with the recess structures.

A method for manufacturing a circuit board includes forming recess structures on a transferring layer; forming a dielectric layer on the transferring layer to form a stacking structure, in which the dielectric layer is at least embedded with the recess structures; bonding the stacking structure a base board by pressing, such that the dielectric layer is in contact with the base board; patterning the dielectric layer, including performing an exposure process on the stacking structure through the transferring layer; and after the exposure process is finished, removing the transferring layer.