A method of making a printed circuit board pallet is provided. The method of making the pallet illustratively includes the steps of: providing a base in a form of a polymer sheet stock; applying a fluid onto the base at selective locations where the pallet will be built-up to a three-dimensional form; depositing a polymer powder onto the base at the selective locations applied with the fluid; removing any excess amounts of the polymer powder not adhered to the fluid; and heating the pallet to fuse the polymer powder together and to the base.

A connection method for a chip and a circuit board includes: placing the circuit board on the chip, the circuit board having a first surface in contact with the chip having a plurality of contacts, and the circuit board having a plurality of through holes aligned with the plurality of contacts respectively; placing a mask on a second surface of the circuit board, the mask having a plurality of openings aligned with the plurality of through holes respectively; covering a surface of the mask with a conductive adhesive to fill the plurality of through holes with the conductive adhesive; and keeping portions of the conductive adhesive that are respectively in the plurality of through holes to be spaced apart from each other. The portions of the conductive adhesive that fill the plurality of through holes remain to provide an electrical connection between the circuit board and the chip.

A method of making a printed circuit board pallet is provided. The method of making the pallet illustratively includes the steps of: providing a base in a form of a polymer sheet stock; applying a fluid onto the base at selective locations where the pallet will be built-up to a three-dimensional form; depositing a polymer powder onto the base at the selective locations applied with the fluid; removing any excess amounts of the polymer powder not adhered to the fluid; and heating the pallet to fuse the polymer powder together and to the base.

Apparatus and methods for forming fine scale structures (4, 4′, 4″, 5, 6, 7, 8) in the surface of a dielectric substrate (3) to two or more depths are disclosed. In an example, the apparatus comprises a first solid state laser (12) arranged to provide a first pulsed laser beam (13), a first mask (16) having a pattern for defining a first set of structures (4, 6, 7, 8) at a first depth, a projection lens (17) for forming a reduced size image of said pattern on the surface (3) of the substrate and a beam scanner arranged to scan said first pulsed laser beam (13) in a two-dimensional raster scan relative to the first pattern to form a first set of structures (4, 6, 7, 5) at a first depth in the substrate, wherein the first or a further solid state laser is arranged to form a second set of structures (8) at a second depth in the substrate (3).

A method of manufacture of a circuit board without annular through-hole rings and thus allowing a higher component density includes a base layer, a first wire pattern layer, and a second wire pattern layer on both sides of the base layer. A portion of the base layer not covered by the first wire pattern layer defines at least one first hole. The circuit board further includes a wire layer. The wire layer includes at least a first portion and a second portion connecting to the first portion. The first portion is filled in the first hole. The second portion is formed on the first portion extending away from the base layer. A diameter of the second portion is less than an aperture diameter of the first hole. The wire layer is electrically conductive between the first wire pattern layer and the second wire pattern layer through the first portion.

Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the method includes forming a molded panel around an EGP array from which a plurality of preformed EGP connections project. One or more Redistribution Layers (RDLs) are produced over the molded panel. The molded panel is then singulated to yield a plurality of FO-WLPs each including a molded package body containing an EGP from the EGP array and one or more of preformed EGP connections.

The present invention comprises a step of forming bump pads on the surface of the substrate, covering the whole surface with a second insulating layer, forming a copper barrier on the surface of a second insulating layer, forming a third insulating layer, and forming a copper layer for an electrical circuit. A mask is formed on the copper layer of the external circuit in such a way that only the region for the cavity is exposed. The cavity is formed by laser-drilling only the surface-exposed area of the third insulating layer. The copper layer at the bottom protects the second insulating layer and bump pads underneath from laser damages. The copper barrier is removed by chemical etch once the laser drill is over. The second insulating layer will be removed via sand blast process, exposing the bump pads which were fabricated in the earlier steps.

A display panel motherboard and a manufacturing method thereof are provided. The display panel motherboard comprises display panel regions (Q1) spaced apart from each other and precut regions (Q2) adjacent to the display panel regions. The manufacturing method comprises forming an electrical insulating layer (102); and removing at least portions of the electrical insulating layer provided on the precut regions (Q2). The method avoids the problem of other patterns offset on the display panel motherboard caused by the larger internal stress within the electrical insulating layer.

A mask including a substrate and a mesh pattern are disclosed along with an electronic device. The mesh pattern, being disposed on the substrate, includes a first striped pattern and a second striped pattern; the first striped pattern includes a first, second, and third section, and the second section is disposed between the first and the third sections; the second striped pattern includes a fourth, fifth, and sixth section, and the fifth section is disposed between the fourth and the sixth sections; the first section has a first extension direction, the fourth section has a second extension direction, and a first included angle is between the first extension direction and the second extension direction; the fifth section and the second section intersect each other while having a second included angle between the two sections, and the second included angle is greater than the first included angle.

Devices and methods are described for reducing etching due to galvanic effect within a printed circuit board that may be used, for example, in a data storage device, such as a card-type data storage device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trance, and that is configured to couple the data storage device to a host device. The contact trace is electrically isolated from the rest of the circuitry during a fabrication process. The contact finger and an exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to an impedance trace though at least one of a component and a bond wire.