Patent classifications
H05K3/02
SYSTEMS INCLUDING A POWER DEVICE-EMBEDDED PCB DIRECTLY JOINED WITH A COOLING ASSEMBLY AND METHOD OF FORMING THE SAME
Systems including power device embedded PCBs coupled to cooling devices and methods of forming the same are disclosed. One system includes a power device embedded PCB stack, a cooling assembly including a cold plate having one or more recesses therein, and a buffer cell disposed within each of the one or more recesses. The cooling assembly is bonded to the PCB stack with a insulation substrate disposed therebetween. The cooling assembly is arranged such that the buffer cell faces the PCB stack and absorbs stress generated at an interface of the PCB stack and the cooling assembly.
SUBSTRATE FOR PRINTED WIRING BOARD AND MULTILAYER SUBSTRATE
A substrate for a printed wiring board includes a base layer, and a copper foil directly or indirectly stacked on at least a part of one or both surfaces of the base layer. The base layer includes a matrix containing a fluororesin as a main component and one or more reinforcing material layers included in the matrix, and a ratio B/A is 0.003 to 0.37, where A is an average thickness of the base layer, and B is an average distance between a surface of the copper foil facing the matrix and a surface of a reinforcing material layer closest to the surface of the copper foil facing the copper foil.
Pattern forming method
A pattern forming method comprises dispensing a curable composition onto an underlayer of a substrate; bringing the curable composition into contact with a mold; irradiating the curable composition with light to form a cured film; and separating the cured film from the mold. The proportion of the number of carbon atoms relative to the total number of atoms in the underlayer is 80% or more. The dispensing step comprises a first dispensing step of dispensing a curable composition (A1) substantially free of a fluorosurfactant onto the underlayer, and a second dispensing step of dripping a droplet of a curable composition (A2) having a fluorosurfactant concentration in components excluding a solvent of 1.1% by mass or less onto the curable composition (A1) discretely.
Touch sensor with auxiliary conductive unit on transparent electrode
A touch sensor includes a substrate, a first touch conductive layer (TCL), a first auxiliary conductive layer (ACL), a second touch conductive layer, and a second auxiliary conductive layer. The first TCL has a first touch conductive trail pattern (TCTP). The first ACL has a lower sheet resistance than the first TCL and a first auxiliary conductive trail pattern (ACTP). The second TCL has a second TCTP. The second ACL has a lower sheet resistance than the second touch conductive layer and a second ACTP. The first and second TCTPs and the first and second ACTPs jointly constitute a touch sensor.
MODULE AND METHOD FOR MANUFACTURING SAME
A module includes a substrate having a first surface and at least one recess on the first surface, and an electronic component mounted on the first surface. The electronic component is connected to the substrate via a plurality of bumps. All of the plurality of bumps are connected to the first surface inside any of the at least one recess. A height of the plurality of bumps is greater than a depth of the at least one recess. When viewed in a direction perpendicular to the first surface, a part of the electronic component is located outside an outer periphery of any recess selected from the at least one recess.
MODULE AND METHOD FOR MANUFACTURING SAME
A module includes a substrate having a first surface and at least one recess on the first surface, and an electronic component mounted on the first surface. The electronic component is connected to the substrate via a plurality of bumps. All of the plurality of bumps are connected to the first surface inside any of the at least one recess. A height of the plurality of bumps is greater than a depth of the at least one recess. When viewed in a direction perpendicular to the first surface, a part of the electronic component is located outside an outer periphery of any recess selected from the at least one recess.
LAMINATED SHEET FOR METAL-CLAD LAMINATE, METHOD OF MANUFACTURING LAMINATED SHEET FOR METAL-CLAD LAMINATE, METAL-CLAD LAMINATE, AND METHOD OF MANUFACTURING METAL-CLAD LAMINATE
An object of the present invention is to provide a laminated sheet for a metal-clad laminate and a method of manufacturing the same, the laminated sheet including: a substrate that includes a liquid crystal polymer or a fluoropolymer; and an adhesive layer, in which adhesiveness with a metal layer formed on the adhesive layer is excellent. Another object of the present invention is to provide a metal-clad laminate and a method of manufacturing the same.
A laminated sheet for a metal-clad laminate includes: a substrate that includes a liquid crystal polymer or a fluoropolymer; an inorganic oxide layer; and an adhesive layer, in which the substrate, the inorganic oxide layer, and the adhesive layer are laminated in this order.
METHOD FOR MANUFACTURING PRINTED WIRING BOARD AND COATING SYSTEM FOR IMPLEMENTING THE METHOD
A method for manufacturing a printed wiring board includes forming a seed layer on a surface of a resin insulating layer, applying liquid resist on the seed layer formed on the surface of the resin insulating layer, drying the liquid resist applied on the seed layer such that a resist layer is formed on the seed layer, applying pressure and heat simultaneously to an entire surface of the resist layer formed on the seed layer, forming a plating resist on the seed layer from the resist layer formed on the seed layer using a photographic technology, forming an electrolytic plating film on part of the seed layer exposed from the plating resist, removing the plating resist from the seed layer, and removing part of the seed layer exposed from the electrolytic plating film.
METHOD FOR MANUFACTURING PRINTED WIRING BOARD AND COATING SYSTEM FOR IMPLEMENTING THE METHOD
A method for manufacturing a printed wiring board includes forming a seed layer on a surface of a resin insulating layer, applying liquid resist on the seed layer formed on the surface of the resin insulating layer, drying the liquid resist applied on the seed layer such that a resist layer is formed on the seed layer, applying pressure and heat simultaneously to an entire surface of the resist layer formed on the seed layer, forming a plating resist on the seed layer from the resist layer formed on the seed layer using a photographic technology, forming an electrolytic plating film on part of the seed layer exposed from the plating resist, removing the plating resist from the seed layer, and removing part of the seed layer exposed from the electrolytic plating film.
Component carrier with blind hole filled with an electrically conductive medium and fulfilling a minimum thickness design rule
A component carrier with a stack including an electrically insulating layer structure and an electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm. A demarcation surface of the plating layer in the blind hole and facing away from the stack extends laterally outwardly from the bottom of the blind hole towards a lateral indentation and extends laterally inwardly from the indentation up to an outer end of the blind hole. An electrically conductive structure fills at least part of a volume between the plating layer and an exterior of the blind hole.