A method of producing a printed circuit board includes providing a base substrate that is a film or plate, has first and second substrate sides and consists partly of an electrically non-conducting organic polymer material, where the first substrate side is covered with a capping metal layer, and regionally removing the capping metal layer, wherein regionally removing the capping metal layer includes applying a mask layer to the capping metal layer, regionally removing the mask layer by a laser so that the first substrate side is divided into at least one first subregion, in which the first substrate side is covered only with the capping metal layer, and into at least one second subregion, in which the first substrate side is covered with the capping metal layer and by the mask layer, and removing the capping metal layer in the at least one first subregion by an etching solution.

Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This “off-device” approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template may be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate.

Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This “off-device” approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template may be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate.

A method for manufacturing a circuit board includes providing a composite material film including a metal film and a polymeric film, disposing a dielectric layer on the polymeric film to form a stacked structure, forming a circuit layer with a contact pad on a substrate, bonding the stacked structure onto the substrate and the circuit layer, and forming a first opening extending through the metal film to form a patterned metal film. The dielectric layer directly contacts the substrate and entirely covers the circuit layer. The method further includes plasma etching the dielectric layer with the patterned metal film as a mask to form a second opening in the dielectric layer and expose the contact pad in the second opening, removing the composite material film, and depositing a conductive material in the second opening to form a conductive blind hole electrically connected to the contact pad.

A method of manufacturing a printed circuit board a includes preparing an insulating substrate on which a first metal layer is formed, stacking a resist laminate having a plurality of layers on the first metal layer, forming an opening exposing a portion of the first metal layer by patterning the stacked resist laminate having the plurality of layers, forming a second metal layer on the exposed portion of the first metal layer, removing the patterned resist laminate having the plurality of layers, and etching at least another portion of the first metal layer.

A printed circuit board includes a first insulating layer, an embedded pattern embedded in one surface of the first insulating layer, a pad formed on the one surface of the first insulating layer, and a post, wherein the center of a side surface of the post is in contact with the one surface of the first insulating layer.

A method of etching an electrically conductive layer structure during manufacturing a component carrier is provided. The method includes subjecting the electrically conductive layer structure to an etching composition having an etchant and a photosensitive compound to thereby form a recess in the electrically conductive layer structure; while, at least for a part of time, irradiating and/or heating the recess. In addition, an apparatus for etching an electrically conductive layer structure during manufacturing a component carrier, an etched electrically conductive layer structure and a component carrier are provided.

Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 μm, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 μm thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.

Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This “off-device” approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template may be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate.

An extremely thin copper foil is provided that enables formation of highly fine different wiring patterns with a line/space (L/S) of 10 μm or less/10 μm or less on two sides of the copper foil and is thus usable as an inexpensive and readily processable substitution for silicon and glass interposers. The extremely thin copper foil includes, in sequence, a first extremely thin copper layer, an etching stopper layer, and the second extremely thin copper layer. Two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 20 nm or less.