A circuit board with conductive wiring which is precisely shaped and sized includes a two-part conductive element, namely a first conductive wiring layer and a second conductive wiring layer, a first cover film and a second cover film. The first conductive wiring layer and the second conductive wiring layer are in direct contact to each other. A projection of the first conductive wiring layer and a projection of the second conductive wiring layer along a direction perpendicular to the circuit board overlap with each other. The first and the second cover films wrap the first and the second conductive wiring layers, respectively.

A glass core wiring substrate incorporating a high-frequency filter having good high-frequency characteristics as a core material and allowing a more efficient arrangement of a conductor in the glass substrate, a module including the same, and a method of manufacturing the glass core wiring substrate incorporating a high-frequency filter. A conductive layer in a glass through a hole in a glass core substrate has a structure in which a hollow cylindrical conductor layer on a side wall of the glass through hole is connected to a cover conductor layer covering one of two openings of the glass through hole. To achieve such a structure, a carrier is attached to one surface of the glass core substrate to cover one of the openings of the glass through hole, and the carrier is peeled off and removed after lamination of the conductor.

A method for fabricating a circuit board comprises preparing an elastomeric substrate having a roughened surface. The elastomeric substrate is stretched before an electrically conductive material is electrolessly deposited onto the roughened surface. A suitable amount of electrically conductive material is deposited onto the elastomeric substrate before the elastomeric substrate is released from its stretch.

A substrate for a printed circuit board according to an embodiment of the present invention includes a base film having insulating properties and a sintered layer formed of a plurality of metal particles, the sintered layer being stacked on at least one surface of the base film, in which a region of the sintered layer extending from an interface between the sintered layer and the base film to a position 500 nm or less from the interface has a porosity of 1% or more and 50% or less.

Example embodiments describe a computer-implemented method for balancing an electrochemical deposition of metal on a PCB substrate; the method including i) obtaining a layout of the metal on the PCB substrate comprising at least one active area having a circuit layout and a balancing area available for the balancing; ii) dividing the substrate area in a plurality of finite elements; iii) determining active metal fractions from the layout for the respective finite elements; iv) determining metal balancing fractions covering respective finite elements in the balancing area based on the active metal fractions in finite elements in the at least one active area surrounding the respective finite element.

A voltage regulator module with a vertical layout structure includes a circuit board assembly, an electroplated region and a magnetic core assembly. The circuit board assembly includes a printed circuit board and at least one switch element. The printed circuit board includes a first surface, a second surface, a plurality of lateral surfaces, an accommodation space and a conductive structure. The switch element is disposed on the first surface. A conduction part is formed on the second surface. The conductive structure is perpendicular to the printed circuit board and disposed within the accommodation space. The electroplated region is formed on the corresponding lateral surface, arranged between the conduction part and the first surface, and electrically connected with the conduction part and the switch element. The magnetic core assembly is accommodated within the accommodation space. Consequently, an inductor is defined by the conductive structure and the magnetic core assembly collaboratively.

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.

Provided is an apparatus for electro-forming. The apparatus for electro-forming includes a plating bath which is a space where a substrate is plated and a clamp disposed within the plating bath and configured to grasp the substrate disposed in a horizontal direction. The apparatus for electro-forming further includes an assembly including an anode spaced above the substrate and connected to an external power supply and a plating solution supply unit spaced above the substrate and configured to supply a plating solution. The apparatus for electro-forming also includes a driving unit configured to reciprocate the assembly in a horizontal direction at a distance from the substrate. The assembly further includes an insulator between the anode and the plating solution supply unit.

Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

A method of manufacturing a printed circuit board includes: forming a resist layer; exposing first areas of the resist layer spaced apart from each other; after exposing the first areas, exposing second areas of the resist layer, the second areas being spaces between the first areas; forming first and second openings spaced apart from each other in the first and second areas by developing the resist layer; and forming a plurality of conductor patterns by filling the first and second openings with conductors.