A method for forming a thermal and electrical path in a PCB may include forming a first removable layer over a top surface of a PCB and a second removable layer over a bottom surface of the PCB. The method may also include milling or laser drilling the PCB from the top surface to form a first cavity extending into the PCB, plating the first side panel plating the first side with a second metal to partially fill the first cavity; and milling or laser drilling from the bottom surface to form a second cavity extending into the PCB, the first cavity in a thermal communication and/or an electrical communication with the second cavity. The method may also include panel plating the first side with a second metal to fill the first cavity and the second side with the second metal to fill the second cavity, and removing the first and second removable layers from the PCB to form the PCB with a thermal and/or an electrical path comprising the first cavity and the second cavity filled with the second metal.

In some embodiments, a manufacturing process includes injection molding a palladium-catalyzed material into a substrate, forming a thin copper film over exterior and exposed surfaces of the substrate; ablating or removing copper film from the substrate to provide first, second and optional third portions of the copper film and ablated sections; electrolytically plating each portion to form metallic-plated portions; and ablating or removing the second portion in order to isolate the first portion. The metallic-plated first portion comprises a circuit portion of a molded interconnect device (MID), and where the metallic-plated third portion comprises a Faraday cage portion of a MID. A soft etching step may be included. A solder resist application step can be added, along with an associated solder resist removal step.

A patterned conductive article 200 includes a substrate 210 including a unitary layer 210-1 and includes a micropattern of conductive traces 220 embedded at least partially in the unitary layer. Each conductive trace extends along a longitudinal direction (y-direction) of the conductive trace and includes a conductive seed layer 230 having a top major surface 232 and an opposite bottom major surface 234 in direct contact with the unitary layer; and a unitary conductive body 240 disposed on the top major surface of the conductive seed layer. The unitary conductive body and the conductive seed layer differ in at least one of composition or crystal morphology. The unitary conductive body has lateral sidewalls 242, 244 and at least a majority of a total area of the lateral sidewalls is in direct contact with the unitary layer.

A method for forming a printed circuit board includes: forming on a substrate a first conductive layer for a first edge connector pin and a first conductive layer for a second edge connector pin, wherein the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin are electrically coupled to one another via a first conductive layer for an electrical bridging element; electroplating a second conductive layer onto both the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin via a plating current conductor; and removing at least a portion of the electrical bridging element to electrically separate the first edge connector pin from the second edge connector pin.

An assembly sheet as a wiring circuit board assembly sheet includes a substrate, a wiring pattern, and a dummy wiring pattern. The substrate includes a product region and a frame region adjacent to the product region. The wiring pattern is located on one side in a thickness direction of the substrate in the product region, and includes a first wiring and a second wiring thicker than the first wiring. The dummy wiring pattern is located on the one side in the thickness direction in the frame region, and includes a first dummy wiring and a second dummy wiring thicker than the first dummy wiring.

A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.

A method of forming a molded interconnect device (MID) is provided. The method includes the steps of performing a molding stage, performing a circuit forming stage, and performing a plate stage. As a part of the molding stage, a palladium-catalyzed material is injection molded into a palladium-catalyzed substrate of a desired shape. As a part of the circuit forming stage, both a metallization step and a circuit patterning step are performed. As a part of the plating stage, both an electrolytic plating step and a circuit isolation step are performed.

Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.

The disclosure relates to an optical transceiver and a manufacturing method thereof. The optical transceiver includes a substrate, a thermal-conductive substrate, a first metal wiring structure, a light-transceiving element and an optical fiber array. The substrate has an opening, and the thermal-conductive substrate is embedded within the opening. The first metal wiring structure is integrally formed on the substrate and the thermal-conductive substrate through an electroplating or a wire-printing process. The light-transceiving element is disposed on the thermal-conductive substrate and is electrically connected to the first metal wiring structure. The optical fiber array is arranged on the thermal-conductive substrate for communication with the light-transceiving element.

A seeded substrate is first prepared. The seeded substrate includes an insulation substrate having a main surface composed of a first region and a second region other than the first region, and a conductive seed layer provided on the first region. Subsequently, a conductive layer is formed on at least the second region to obtain a first treated substrate. An insulation layer is then formed on the first treated substrate. The seed layer is then exposed. A metal layer is then formed on the surface of the seed layer. Here, a voltage is applied between the anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing solution being disposed between the second treated substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the insulation layer and the conductive layer are removed.