A circuit board having a plurality of conductive layers including a first conductive layer and a second conductive layer is provided. The circuit board includes a plurality of non-conductive layers in-between respective conductive layers of the plurality of conductive layers. The plurality of non-conductive layers include at least a first non-conductive layer disposed between the first conductive layer and the second conductive layer. At least one collapsed stud bump extends at least partially through the first non-conductive layer to electrically couple the first conductive layer to the second conductive layer.

A component carrier including a stack with a plurality of electrically insulating layer structures and/or a plurality of electrically conductive layer structures, and a component embedded in the stack, wherein at least a portion of a side wall of the component is exposed.

An extremely thin copper foil is provided that enables formation of highly fine different wiring patterns with a line/space (L/S) of 10 μm or less/10 μm or less on two sides of the copper foil and is thus usable as an inexpensive and readily processable substitution for silicon and glass interposers. The extremely thin copper foil includes, in sequence, a first extremely thin copper layer, an etching stopper layer, and the second extremely thin copper layer. Two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 20 nm or less.

A reel-to-reel method to laser-ablate a circuitry pattern on the fly in a reel-to-reel machine as part of a process to fabricate a printed flexible circuit. The laser ablation method includes using an appropriate laser to irradiate a metal sheet thus ablating the edges of an intended circuitry pattern. Slugs can be removed by using an optional sacrificial liner, and the slugs can be optionally ablated into smaller parts first. The laser ablation can also include an optional method of creating tie bars to provide structural support to the web of circuitry patterns.

A multilayer resin substrate includes resin layers that are laminated, a first copper foil on the resin layers and including first and second main surfaces having first and second surface roughnesses, respectively, and a second copper foil on the resin layers and including third and fourth main surfaces having third and fourth surface roughnesses, respectively. A distance between the first main surface and the second copper foil is shorter than a distance between the second main surface and the second copper foil. When the first, second, third, and fourth surface roughnesses are denoted as SR1, SR2, SR3, and SR4 respectively, a relationship SR1<SR3≤SR4<SR2 is satisfied.

The method for producing a laminate having a patterned metal foil includes masking the whole surface of a first metal foil in a laminate having the first metal foil, a first insulating resin layer having a thickness of 1 to 200 μm and a second metal foil laminated in this order, and patterning the second metal foil.

A multilayer substrate and a manufacturing method thereof are disclosed. The multilayer substrate includes two or more dielectric layers laminated in sequence; a public line disposed at a top or bottom dielectric layer of the two or more dielectric layers; and two or more first through hole pillars respectively each embedded in a respective one of the dielectric layers, and the first through hole pillars are connected in cascade and then connected with the public line.

A method includes providing a layer of non-conductive material having a conductive electroplating seed layer formed on a surface thereof; applying a photoresist layer over the surface of the conductive electroplating seed layer; and defining wiring channels in the photoresist resist layer. The method includes electroplating a conductive material in the defined wiring channels; adhering a non-conductive layer over the photoresist layer and the plated conductive material in the wiring channels; and removing the layer of non-conductive material and the conductive electroplating seed layer.

A lamination circuit board structure lamination circuit board structure includes a printed circuit board substrate including conductive wiring traces on at least a first wiring face, a prepreg layer formed over the first wiring face, and a patch having an area smaller than 1,000 mm.sup.2. The patch includes conductive wiring traces formed on a wiring face and is laminated to the printed circuit board substrate over the prepreg layer, oriented with the wiring face in contact with and pressed into the prepreg layer. Portions of the prepreg layer fill interstices between the conductive wiring traces.

The electronic circuit device according to the present invention including the wiring layer 13 including a plurality of the metal wirings, the photosensitive resin layer 21 made of the photosensitive resin arranged on the wiring layer 13, and the first electronic circuit element 33 arranged in the photosensitive resin layer 21. In this electronic circuit device, a plurality of opening 41 for exposing a part of the wiring layer 13 is formed on the photosensitive resin layer 21, and further, together with three-dimensionally connected to the first electronic circuit element 33, the re-distribution layer 42 on the first electronic circuit element including a plurality of the metal wirings which is three-dimensionally connected via a plurality of openings to a part of the wiring layer 13, and the first external connection terminal 51 connected to the re-distribution layer 42 are formed.