The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.

A method of forming a plug for a semiconductor device and a semiconductor device thereof are disclosed. The proposed method of forming a plug for a semiconductor device, wherein the semiconductor device includes a deep trench (DT) structure and a storage node configured in the DT structure, comprising: (a) filling a single film in the DT structure and to cover the storage node; and (b) etching back the single film to form the plug located in the DT structure and around the storage node, wherein the single film forms a liner of a single type.

The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate having a fin portion protruding from a surface of the semiconductor substrate; disposing a semiconductive material over the semiconductor substrate and conformal to the fin portion; disposing a conductive material over the semiconductive material; disposing an insulating material over the conductive material; disposing a patterned photoresist over the insulating material; applying an electric field at a first predetermined angle toward a plasma to remove a portion of the insulating material exposed through the patterned photoresist to form an insulating layer, to remove a portion of the conductive material under the portion of the insulating material to form a conductive layer, and to remove a portion of the semiconductive material under the portion of the insulating material to form a semiconductive layer; and removing the patterned photoresist from the insulating layer.

The present application provides a memory device having a memory cell with reduced protrusion protruding from the memory cell. The memory device includes a semiconductor substrate having a fin portion protruding from a surface of the semiconductor substrate; a semiconductive layer disposed conformal to the fin portion; a conductive layer disposed over the semiconductive layer; an insulating layer disposed over the conductive layer; and a protrusion including a first protruding portion laterally protruding from the semiconductive layer and along the surface, a second protruding portion laterally protruding from the conductive layer and over the first protruding portion, and a third protruding portion laterally protruding from the insulating layer and over the second protruding portion, wherein the protrusion has an undercut profile.

The present disclosure is in the field of semiconductor devices, in particular, to a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate with a trench extending in a direction of the substrate; a capacitor fabricated in the trench, the capacitor includes a lower electrode disposed on an inner wall of the trench, a dielectric combination layer disposed on the lower electrode, and an upper electrode disposed on the dielectric combination layer; the dielectric combination layer includes a stacked structure composed of a nitride layer and an oxide layer. The device can increase the capacitance of the capacitor significantly and reduce the occurrence of charge leakage, thereby improving the electrical performance of the semiconductor memory device.

A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10.sup.−4 Ωcm to 1.0×10.sup.4 Ωcm or a sheet resistance in a range from 1.0×10.sup.2Ω/□ to 1.0×10.sup.10Ω/□.

A semiconductor structure includes a substrate; at least one layer of memory structure formed on the substrate, in which each layer of memory structure comprises a bit line structure and a plurality of capacitor structures symmetrically distributed on both sides of the bit line structure, the plurality of capacitor structures and the bit line structure extend in a first direction parallel to the substrate surface; a plurality of word line structures formed in the at least one layer of memory structure, which pass through the at least one layer of memory structure and extend in a second direction perpendicular to the substrate surface.

A semiconductor structure includes: a substrate; a plurality of active layers arranged on the substrate and spaced apart from each other; and a plurality of bit lines, spaced apart from each other in a first direction and extending in a second direction. A first portion of each bit line covers side surfaces of respective active layers of the plurality of active layers, and a second portion of each bit line is located in the respective active layers. The first direction and the second direction are parallel to a surface of the substrate, and the first direction intersects with the second direction.

The invention discloses a dynamic random access memory (DRAM) device and a method of fabricating such DRAM device. The DRAM device according to the invention includes a plurality of bit lines formed on a semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of transistors formed between the first isolation stripes and the second isolation stripes, a plurality of word lines, and a plurality of capacitors formed above the first isolation stripes and the second isolation stripes. The semiconductor substrate defines a longitudinal direction, a transverse direction, a normal direction, a plurality of columns in the longitudinal direction, and a plurality of rows in the transverse direction. The first isolation stripes and the second isolation stripes extend in the longitudinal direction. Each transistor corresponds to one of the columns and one of the rows. The transistors on one side of each first isolation stripe and the transistors on the other side of said one first isolation stripe are staggeredly arranged. Each word line corresponds to one of the columns and connects the gate conductors of the transistors along the corresponding column. Each capacitor corresponds to one of the transistors and connects the source region of the corresponding transistor.

A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.