A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

A mask-programmable read only memory (ROM) is provided. The mask ROM includes first and second unit cells; an isolation gate electrode that isolates the first unit cell and the second unit cell; and a bit line that crosses the first and second unit cells. The first unit cell includes: a first source contact and a first bit line contact which are disposed on a semiconductor substrate; and a first gate electrode disposed between the first source contact and the first bit line contact. The second unit cell includes: a second source contact and a second bit line contact which are disposed on the semiconductor substrate; a second gate electrode disposed between the second source contact and the second bit line contact; and a via structure electrically connected to the second bit line contact. The bit line is connected to the via structure of the second unit cell.

A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

Provided is a read-only memory (ROM) device. The ROM device comprises a substrate that has a plurality of vertical transport field effect transistors (VFETs). The ROM device further comprises an un-activated semiconductor layer provided on each VFET. The un-activated semiconductor layer includes implanted dopants that have not been substantially activated.

The present application discloses a method for fabricating a semiconductor device The method includes providing a substrate; forming a channel region in the substrate; forming a gate dielectric layer on the channel region; forming a gate bottom conductive layer on the gate dielectric layer; forming first impurity regions on two ends of the channel region; forming first contacts on the first impurity regions; forming programmable insulating layers on the first contacts; forming a gate via on the gate bottom conductive layer; and forming a top conductive layer on the gate via and the programmable insulating layers.

In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

A layout structure of a small-area one time programmable (OTP) memory using a complementary FET (CFET) is provided. The OTP memory has transistors TP as a program element and transistors TS as a switch element. The transistors TP are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The transistors TS are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The OTP memory of two bits is implemented in a small area.

A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a channel region positioned in the substrate, first impurity regions positioned in the substrate and respectively positioned on two ends of the channel region, a gate dielectric layer positioned on the channel region, a gate bottom conductive layer positioned on the gate dielectric layer, first contacts respectively positioned on the first impurity regions, programmable insulating layers respectively positioned on the first contacts, a top conductive layer positioned on the programmable insulating layers and electrically coupled to the gate bottom conductive layer.

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitline. The integrated circuit may include a memory cell array having a plurality of memory cells. The integrated circuit may include a plurality of via paths coupling each of the memory cells to the bitline. The integrated circuit may include one or more open paths formed to decouple one or more memory cells from their corresponding via path to the bitline.