An integrated circuit includes an array of devices including a physically unclonable function (PUF) for chip authentication. A logic pattern is stored in the devices. The logic pattern is determined in accordance with processing variations during manufacture of the array. The logic pattern is represented with a first state for one or more devices with contact shorts and a second state with one or more devices without contact shorts.

A semiconductor device including a first nanosheet stack of two memory cells including a lower nanosheet stack on a substrate including alternating layers of a first work function metal and a semiconductor channel material vertically aligned and stacked one on top of another, and an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material vertically aligned and stacked one on top of another, the upper nanosheet stack vertically aligned and stacked on the lower nanosheet stack, where a first memory cell of the two memory cells including the lower nanosheet stack includes a first threshold voltage and a second memory cell of the two memory cells including the upper nanosheet stack includes a second threshold voltage, where the first threshold voltage is different than the second threshold voltage. Forming a semiconductor device including a first nanosheet stack of two memory cells.

An integrated circuit includes an array of devices with a logic pattern to implement a physically unclonable function (PUF) for chip authentication. The logic pattern is determined in accordance with processing variations during the manufacturing. The array of devices includes one or more components having a first state and one or more components having a second state. A combination of the first and second states provides the logic pattern.

At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

An integrated circuit includes an array of devices with a logic pattern to implement a physically unclonable function (PUF) for chip authentication. The logic pattern is determined in accordance with processing variations during the manufacturing. The array of devices includes one or more components having a first state and one or more components having a second state. A combination of the first and second states provides the logic pattern.

An integrated circuit includes an array of devices including a physically unclonable function (PUF) for chip authentication. A logic pattern is stored in the devices. The logic pattern is determined in accordance with processing variations during manufacture of the array. The logic pattern is represented with a first state for one or more devices with contact shorts and a second state with one or more devices without contact shorts.

At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

A one-time programmable memory (OTP) is provided that includes a combined word line programming line (WL-PL). The OTP includes a programmable transistor having a first threshold voltage and a first breakdown voltage, and a pass transistor having a second threshold voltage and a second breakdown voltage. The combined WL-PL is electrically connected to respective gate electrodes of both the programmable transistor and the pass transistor so that both receive the same control voltage. The second gate electrode has a work function that is greater than that of the first gate electrode, so that the second gate breakdown voltage is greater than the first gate breakdown voltage, which enables the use of the combined WL-PL.

A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.