A preparation method for a flat cell ROM device, comprising the steps of: providing a substrate, and forming a P well on the substrate; forming a photomask layer on the P well and performing photoetching to form an injection window; injecting P-type ions in the formed injection window to form a P-type region; injecting N-type ions in the injection window so as to form an N-type region on the P-type region; and forming a gate oxide layer and a poly-silicon gate so as to complete the preparation of a device.

A semiconductor storage device includes first and second memory cells adjacent to each other in the X direction, each of the memory cells having a program transistor and a switch transistor. First and second nanosheets, which are to be channel regions of the program transistors, are exposed from first and second gate interconnects, respectively, at faces on the sides opposed to each other in the X direction. Third and fourth nanosheets, which are to be channel regions of the switch transistors, are exposed from third and fourth gate interconnects, respectively, at faces on the sides opposed to each other in the X direction.

A nonvolatile semiconductor storage device includes a plurality of cell transistor pairs including a pair of cell transistors sharing a first node connected to a bit line or a source line, and a dummy gate line laid in parallel with gate lines of the cell transistors, the dummy gate line applying an off voltage to a dummy transistor between the cell transistor pairs. The gate lines and the dummy gate line may be laid at equal intervals. A plurality of impurity diffusion layers corresponding to the first node and second nodes of the cell transistors may be formed at equal intervals in a continuous active region.

An integrated circuit includes a read only memory (ROM) cell which includes an on-cell. The on-cell includes: a first source/drain region and a second source/drain region; a frontside contact between the first source/drain region and a bit line on a front side of the on-cell; and a backside contact between the second source/drain region and a power line on a back side of the on-cell. The bit line is configured to provide a bit line signal to the on-cell, and the power line is configured to provide a power supply voltage signal to the on-cell. The bit line and the power line are vertically aligned with each other.

A high-speed multi-write read only memory array includes word lines, select lines, bit lines, and sub-memory arrays. There are a first word line, a first select line, a second select line, a first bit line, a second bit line, a third bit line, and a fourth bit line. Each sub-memory array includes a first memory cell coupled to the first word line, the first select line, and the first bit line, a second memory cell coupled to the first word line, the first select line, and the second bit line, a third memory cell coupled to the first word line, the second select line, and the third bit line, and a fourth memory cell coupled to the first word line, the second select line, and the fourth bit line.

A read-only memory (ROM) array includes first through fourth rows of ROM bits including respective first through fourth adjacent active areas. Each of the first through fourth rows of ROM bits includes a total of four adjacent ROM bits positioned along the corresponding one of the first through fourth active areas, each ROM bit of the total of four ROM bits of each row of ROM bits includes two source/drain (S/D) regions in the corresponding active area, and three of the S/D regions of each row of ROM bits are shared by the four ROM bits.

The disclosure describes a multi-write read-only memory array and a read-only memory thereof. The read-only memory array includes common-source lines, word bit lines, and sub-memory arrays. The common-source lines include a first common-source line and a second common-source line. The word bit lines include a first word bit line and a second word bit line. Each sub-memory array includes four memory cells. Each memory cell is coupled to the word bit line and the common-source line. The read-only memory includes a field-effect transistor and a capacitor. The source of the field-effect transistor is coupled to the word bit line. The drain of the field-effect transistor is coupled to the common-source line. The capacitor is coupled to the gate of the field-effect transistor and the word bit line.

A semiconductor storage device includes first and second memory cells adjacent to each other in the X direction, each of the memory cells having a program transistor and a switch transistor. First and second nanosheets, which are to be channel regions of the program transistors, are exposed from first and second gate interconnects, respectively, at faces on the sides opposed to each other in the X direction. Third and fourth nanosheets, which are to be channel regions of the switch transistors, are exposed from third and fourth gate interconnects, respectively, at faces on the sides opposed to each other in the X direction.

A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.

A memory device is provided. The memory device includes a plurality of read only memory (ROM) cells formed in a device layer. Each of the ROM cells includes a gate structure of a transistor coupled to a word line on a front side of the device layer, a first source/drain feature of the transistor coupled to a bit line, and a second source/drain feature of the transistor. The ROM cells include a plurality of first cells corresponding to a first logic value and a plurality of second cells corresponding to a second logic value complementary to the first logic value. In the first cell, the second source/drain feature of the transistor is coupled to a VSS line extending along the same orientation as the bit line. The device layer is formed between the bit line and the VSS line.