An inductive device includes a first set of conductive lines, a second set of conductive lines, and conductive pillars connecting the first set of conductive lines to the second set of conductive lines to form an integrated inductor. The inductive device also includes one or more magnetic layers extending along a length of the integrated inductor and within an aperture of the integrated inductor.

A semiconductor package includes a substrate, a semiconductor die, metal interconnects, the semiconductor die being mounted to the substrate via the metal interconnects, an inductor mounted to the substrate, a magnetic material encapsulating the semiconductor die, the inductor, and the metal interconnects, the magnetic material including metal particles suspended in a first insulation material, and a second insulation material covering the magnetic material, wherein the second insulation material is substantially free of metal particles.

The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

A semiconductor element includes a main body having an obverse surface and a reverse surface facing away from each other in a first direction and a plurality of electrodes disposed on the obverse surface and electrically conducting to the main body. The main body has a first side surface facing in the second direction x. The first side surface includes a first edge that is farthest from the reverse surface. The main body has a second side surface connected to the first edge and located between the first side surface and the obverse surface in the first direction z. The second side surface overlaps with the reverse surface as viewed in the first direction z. The surface roughness of the first side surface differs from that of the second side surface.

A semiconductor device includes a substrate; a first terminal and a second terminal; and a conductor arranged on the substrate between the first terminal and the second terminal to constitute an inductor shaped for forming a first loop and a second loop. A first crossing of the conductor with itself is present between the first loop and the second loop. The first loop and the second loop define a first enclosed area and a second enclosed area, respectively. The first enclosed area is smaller than the second enclosed area.

A semiconductor device including: a semiconductor substrate; a seed layer that is formed on the semiconductor substrate; and wiring that is formed on the seed layer and includes parallel row portions that are arranged at intervals from each other, and in which penetration passages that penetrate the parallel row portions in a direction in which the parallel rows lined up are formed in the parallel row portions.

A semiconductor package includes a wiring structure including at least one first wiring layer and at least one first insulating layer, a semiconductor chip overlapping the wiring structure in a vertical direction, a second insulating layer overlapping the wiring structure in the vertical direction and including a cavity, an inductor in the cavity and electrically connected to the semiconductor chip, a lead-out pillar extending from one surface of the inductor facing the wiring structure and electrically connecting the inductor and the semiconductor chip, and an encapsulant encapsulating the inductor, wherein the inductor includes an insulating body and a coil portion in the insulating body, and configured to output a magnetic field in a direction, different from the vertical direction, and a region on one surface of the insulating body not overlapping the lead-out pillar is in direct contact with the encapsulant or the at least one first insulating layer.

A device includes a first region on a substrate including a first integrated circuit, a second region on the substrate including a second integrated circuit, and a third region between the first region and the second region on the substrate. At least one of the first region and the second region includes at least one pattern that provides galvanic isolation between a first integrated circuit and a second integrated circuit on the substrate.

A number of semiconductor die with Group III nitride-based amplifier circuits are described. In one example, the semiconductor die includes a first Group III nitride-based transistor having a first output contact. The semiconductor die includes a second Group III nitride-based transistor having a second output contact. The semiconductor die includes an output combiner inductor on the semiconductor die. The output combiner inductor may be coupled to the first output contact and to the second output contact. The output combiner inductor may further be coupled to a radio frequency (RF) output interface for the semiconductor die.

A semiconductor device includes a semiconductor chip that has a main surface, an insulating layer that is formed on the main surface, a functional device that is formed in at least one among the semiconductor chip and the insulating layer, a low potential terminal that is formed on the insulating layer and is electrically connected to the functional device, a high potential terminal that is formed on the insulating layer at an interval from the low potential terminal and is electrically connected to the functional device, and a seal conductor that is embedded as a wall in the insulating layer such as to demarcate a region including the functional device, the low potential terminal and the high potential terminal from another region in plan view, and is electrically separated from the semiconductor chip, the functional device, the low potential terminal and the high potential terminal.