To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

A method of manufacturing a semiconductor device is provided, including: forming a first conductive type lightly doped region in the epitaxial layer; forming a first conductive type heavily doped region and a second conductive type heavily doped region in the epitaxial layer on the first conductive type lightly doped region, in which the neighboring first conductive type heavily doped regions are spaced apart by the second conductive type heavily doped region; disposing the mask on the second conductive type heavily doped region; disposing a spacer on a sidewall of the mask; doping a first conductive type dopant in the first conductive type lightly doped region to form an anti-breakdown region; removing the mask and forming a trench extending into the second conductive type heavily doped region, first conductive type lightly doped region and the epitaxial layer; and removing the spacer.

A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a substrate, forming a first insulating film around the fin-shaped semiconductor layer, and a first metal film is formed around the first insulating film. A pillar-shaped semiconductor layer is formed on the fin-shaped semiconductor layer and a gate insulating film is formed around the pillar-shaped semiconductor layer. A gate electrode is formed around the gate insulating film, the gate electrode being made of a third metal, and a gate line is connected to the gate electrode. A second insulating film is formed around a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second metal film is formed around the second insulating film.

A semiconductor device includes a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a first metal film around the first insulating film. A pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer, and a gate insulating film is around the pillar-shaped semiconductor layer. A gate electrode is around the gate insulating film and is made of a third metal. A gate line is connected to the gate electrode, and an upper portion of the fin-shaped semiconductor layer and the first metal film are electrically connected to each other.

The present invention discloses a method of forming a high voltage junctionless device with drift region. The drift region formed between the semiconductor channel and the dielectric layer enables the high voltage junctionless device to exhibit higher punch-through voltages and high mobility with better performance and reliability.

Vertical field effect transistor (FET) device with tunable bandgap source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a vertical FET device includes a lower source/drain region formed on a substrate, a vertical semiconductor fin formed on the lower source/drain region, and an upper source/drain region formed on an upper region of the vertical semiconductor fin. The lower source/drain region and vertical semiconductor fin are formed of a first type of III-V semiconductor material. The upper source/drain region is formed of a second type of III-V semiconductor material which comprises the first type of III-V semiconductor material and at least one additional element that increases a bandgap of the second type of III-V semiconductor material of the upper source/drain region relative to a bandgap of the first type of III-V compound semiconductor material of the lower source/drain region and the vertical semiconductor fin.

Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300 C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000 C.-hours to activate the implanted ions.

A tunneling field-effect transistor with an insulated planar gate adjacent to a heterojunction between wide-bandgap semiconductor, such as silicon carbide, and either a narrow band gap material or a high work function metal. The heterojunction may be formed by filling a recess on a silicon carbide planar substrate, for example by etched into an epitaxially grown drift region atop the planar substrate. The low band gap material may be silicon which is deposited heterogeneously and, optionally, annealed via laser treatment and/or doped. The high work function metal may be tungsten, platinum, titanium, nickel, tantalum, or gold, or an alloy containing such a metal. The plane of the gate may be lateral or vertical. A blocking region of opposite doping type from the drift prevents conduction from the filled recess to the drift other than the conduction though the heterojunction.

A semiconductor device includes a first n type layer and a second n type layer that are sequentially disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench that are disposed at the second n type layer and are spaced apart from each other; a p type region surrounding a lateral surface and a lower surface of the first trench; an n+ type region disposed on the p type region and the second n type layer; a gate insulating layer disposed in the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ type region disposed in the first trench; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate.

A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface.