H10D62/8271

METHOD OF FORMING PN HETEROJUNCTION BETWEEN NICKEL OXIDE AND GALLIUM OXIDE AND SCHOTTKY DIODE MANUFACTURED BY THE METHOD

Method of forming pn heterojunction between nickel oxide and gallium oxide disclosed. The method includes forming a trench by etching an n-type gallium oxide epitaxial layer epitaxially grown on an n-type gallium oxide substrate using an etch mask, forming a p-type nickel oxide region on the bottom of the trench by sputtering a nickel oxide target on the n-type gallium oxide epitaxial layer in a mixed gas atmosphere of argon and oxygen, and forming a nickel layer on the p-type nickel oxide region by sputtering a nickel target on the n-type gallium oxide epitaxial layer in an argon gas atmosphere.

EPITAXIAL OXIDE MATERIALS, STRUCTURES, AND DEVICES
20250275302 · 2025-08-28 · ·

In some embodiments, a semiconductor structure includes a single crystal substrate, a first epitaxial oxide layer on the single crystal substrate, and a second epitaxial oxide layer on the single crystal substrate. The first epitaxial oxide layer can include a first oxide material with a cubic crystal symmetry. The second epitaxial oxide layer can include a second oxide material with a monoclinic crystal symmetry. The second epitaxial oxide layer can be elastically strained to the first epitaxial oxide layer. The substrate can include MgO, MgAl.sub.2O.sub.4, or -Ga.sub.2O.sub.3. The first epitaxial oxide layer can include MgO with a cubic crystal symmetry oriented in the (100) direction, and the second epitaxial oxide layer can include -Ga.sub.2O.sub.3 oriented in the (100) direction, where there is a 45 rotation around the (100) direction between the MgO and the -Ga.sub.2O.sub.3 crystal structures.

P-TYPE SPINEL STRUCTURES AS A P-N HETEROEPITAXIAL INTERFACE TO B-GA2O3

Spinel and gallium oxide (Ga.sub.2O.sub.3) p-n heteroepitaxial interfaces and methods of making the same are presented. In embodiments, a method of manufacturing spinel structures includes depositing, via off-axis sputtering, an epitaxial layer of p-type spinel on a gallium oxide (Ga.sub.2O.sub.3) substrate, thereby creating a p-n heteroepitaxial interface between the p-type spinel and the Ga.sub.2O.sub.3 substrate. In implementations, a semiconductor device includes a Ga.sub.2O.sub.3 substrate; a p-type spinel epitaxial layer formed directly on a surface of the Ga.sub.2O.sub.3 substrate, thereby forming a p-n heteroepitaxial interface; and electrodes.

PLASMA-FREE ETCHED B-GA2O3-NIO MERGED PIN SCHOTTKY DIODE WITH HIGH-VOLTAGE STRESS RELIABILITY

A (Ga.sub.2O.sub.3)-nickel oxide (NiO) heterojunction device and method of making the same are presented. In implementations, the method includes: providing a Ga.sub.2O.sub.3 base including a Ga.sub.2O.sub.3 substrate with an n-type Ga.sub.2O.sub.3 epitaxial layer thereon; forming NiO-filled internal trenches and an NiO-filled peripheral trench in the n-type Ga.sub.2O.sub.3 epitaxial layer using a plasma-free etching process; forming at least one junction termination extension (JTE) structure about the periphery of the n-type Ga.sub.2O.sub.3 epitaxial layer; depositing an anode over the NiO filled interior trenches, over portions of the NiO-filled peripheral trench, and over portions of the JTE structure; and depositing a cathode over a bottom surface of the Ga.sub.2O.sub.3 substrate, thereby forming the Ga.sub.2O.sub.3NiO heterojunction device, wherein the Ga.sub.2O.sub.3NiO heterojunction device is formed without the use of plasma-etching and is free of plasma-etching damage.

Semiconductor device and method of manufacturing semiconductor device

The present disclosure relates to a semiconductor device including an n-type gallium oxide semiconductor layer that has a center region and a peripheral region having a lower donor density than the center region, an electrode layer that is laminated on the n-type gallium oxide semiconductor layer, and forms Schottky junction with the n-type gallium oxide semiconductor layer in the center region as viewed from a lamination direction, and a first p-type nickel oxide semiconductor layer that is laminated on the n-type gallium oxide semiconductor layer such that the first p-type nickel oxide semiconductor layer is partially positioned between the n-type gallium oxide semiconductor layer and the electrode layer, and has an outer peripheral end portion on a peripheral region side in the peripheral region as viewed from the lamination direction.

THERMODYNAMIC STABILIZATION LAYERS FOR OXIDE SEMICONDUCTOR HETEROJUNCTIONS

Described herein are the insertion of thermodynamic stabilization layers between p- and n-type oxide heterojunction semiconductors that allow for operation and stability at high temperatures, for example, greater than 500 C. The stabilization layer may have a spinel crystal structure and the surrounding layers may be coincidence site lattice matched. An example formulation is n-type Ga.sub.2O.sub.3 and p-type NiO separated by a spinel NiGa.sub.2O.sub.4 stabilization layer.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
20250311259 · 2025-10-02 ·

A method of manufacturing a semiconductor device including a tin oxide semiconductor having a pn junction between a source electrode and a drain electrode, the method including, changing a conductivity type of a portion of a layer made of the tin oxide semiconductor to form the pn junction.

METHOD FOR CONTROLLING CARRIER CONCENTRATION OF NICKEL OXIDE AND SCHOTTKY DIODE MANUFACTURED BY THE METHOD

A method for controlling the carrier concentration of nickel oxide is disclosed. The method for controlling the carrier concentration of nickel oxide comprises the steps of: preparing an n-type gallium oxide substrate on which an n-type gallium oxide epitaxial layer is formed; sputtering a nickel oxide target in a first mixed gas atmosphere of argon and oxygen, thereby depositing a first p-type nickel oxide layer on the n-type gallium oxide epitaxial layer, and sputtering the nickel oxide target in a second mixed gas atmosphere of argon and oxygen, thereby depositing a second p-type nickel oxide layer on the n-type gallium oxide epitaxial layer.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A leakage current is suppressed. A semiconductor device includes: a first anode electrode formed in a part of an upper surface of a gallium oxide layer of a first conductivity type; a semiconductor layer of a second conductivity type to cover a part of the gallium oxide layer and at least a part of the first anode electrode; and a second anode electrode to cover the semiconductor layer, wherein a plurality of trenches is formed in a surface layer of the gallium oxide layer, the first anode electrode is formed in the surface layer of the gallium oxide layer, the first anode electrode not overlapping the trenches in a plan view, and the semiconductor layer covers the gallium oxide layer in an inner portion of the trenches.