A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (PLL) circuit or at least one Digital-Lock-Loop (DLL) circuit.

A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, disposed over the third metal layer; a third level including a plurality of third transistors, disposed over the second level; a via disposed through the second and third levels; a fourth metal layer disposed over the third level; a fifth metal layer disposed over the fourth metal layer; and a fourth level including a second single crystal silicon layer and is disposed over the fifth metal layer, where each of the plurality of second transistors includes a metal gate, and the via has a diameter of less than 450 nm.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.

A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.

A device includes a vertical transistor comprising a first buried layer over a substrate, a first well over the first buried layer, a first gate in a first trench, wherein the first trench is formed partially through the first buried layer, and wherein a dielectric layer and the first gate are in the first trench, a second gate in a second trench, wherein the second trench is formed partially through the first buried layer, and wherein the second trench is of a same depth as the first trench, a first drain/source region and a second drain/source region formed on opposite sides of the first trench and a first lateral transistor comprising a second buried layer formed over the substrate, a second well over the second buried layer and drain/source regions over the second well.

A semiconductor component including: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.

Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.

A p-type field effect transistor includes a pair of spacers over a substrate top surface. The p-type field effect transistor includes a channel recess cavity in the substrate top surface between the pair of spacers. The p-type field effect transistor includes a gate stack with a bottom portion in the channel recess cavity. The p-type field effect transistor includes a source/drain (S/D) recess cavity including a bottom surface and sidewalls below the substrate top surface, wherein the S/D recess cavity includes a portion extending below the gate stack. The p-type field effect transistor includes a strained material filling the S/D recess cavity. The p-type field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the bottom surface and sidewalls of the S/D recess cavity. The S/D extension includes a portion between the gate stack and the S/D recess cavity.