A semiconductor structure including first source drain regions and second source drain regions arranged above a backside dielectric layer, and a buffer layer physically separating at least one of the second source drain regions from the backside dielectric layer, where at least one of the first source drain regions is in direct contact with the backside dielectric layer.

A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.

A semiconductor device, a semiconductor chip and manufacturing methods thereof are provided. The semiconductor device includes: channel structures, vertically spaced apart from one another; a gate structure, intersecting the channel structures and wrapping around each of the channel structures; source/drain structures, in lateral contact with the channel structures from opposite sides of the channel structures; and protection structures, separately disposed along a bottom surface of the gate structure, wherein the channel structures are located between the protection structures, and the protection structures comprise a semiconductor material.

To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

A nitride semiconductor device includes: an electron transit layer; an electron supply layer that is formed on the electron transit layer and that has a band gap which is larger than that of the electron transit layer; a dielectric layer that is formed on the electron supply layer; and an electrode that has a contact part which is in electrical contact with the electron supply layer via at least an opening passing through the dielectric layer. The contact part has: an inclined surface that is inclined so as to decrease in width toward the electron transit layer; a tip surface that is in contact with the bottom face of the opening; and a curved surface that is provided between the tip surface and the inclined surface and that is curved so as to protrude toward the electron transit layer.

A semiconductor device includes a semiconductor layer including a first surface and a second surface opposite to the first surface; a source trench formed in the semiconductor layer and including a side wall that is continuous with the second surface; an insulation layer formed on the second surface of the semiconductor layer; an embedded electrode arranged in the source trench and insulated from the side wall of the source trench by the insulation layer; a source interconnection formed on the insulation layer; and a source contact plug electrically connecting the source interconnection to the semiconductor layer. The source contact plug contacts the embedded electrode, and the source contact plug contacts the semiconductor layer via a part of the side wall of the source trench.

A power semiconductor device comprises a semiconductor body, a gate electrode, and an extraction electrode, wherein the semiconductor body comprises a source region of a first conductivity type, well region of a second conductivity type different from the first conductivity type at the gate electrode, a drift region which is of the first conductivity type, and a barrier region which is of the first conductivity type, the barrier region is located between the drift region and the extraction electrode.

A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.

A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.