A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes first to fifth circuits. Each of the first to fourth circuits includes first and second cells, a sixth circuit, first and second current generation circuits, a first input terminal, and a second output terminal. The first circuit to the fourth circuit are electrically connected to each other in a ring, and the first circuit is electrically connected to the fifth circuit. In each of the first to fourth circuits, the first cell is electrically connected to the second cell through the first wiring, the first current generation circuit, and the third wiring, and is electrically connected to the first input terminal and the sixth circuit through the second wiring. The second cell is electrically connected to the first output terminal through the second current generation circuit. Note that the first current generation circuit functions as a current mirror circuit, and the second current generation circuit functions as an arithmetic circuit of a function system. The first cell performs an arithmetic operation of a product, and the second cell retains the result of the arithmetic operation.

The present disclosure provides a circuitry electrically connected to a battery, a regulation circuit and an operating method thereof. The circuitry includes a regulation circuit, a first transistor set and a second transistor set. The regulation circuit includes a first node, a second node and a third node. The first node electrically connects to a power source, and the second node electrically connects to a cathode of the battery. When the circuitry is operated in a first mode, the first node electrically connects to the third node through the first transistor set to create a first path from the first node to the second node. When the circuitry is operated in a second mode, the second node electrically connects to the third node through the second transistor set to create a second path from the second node to the first node.

A semiconductor device includes: one or more semiconductor modules arranged in a row; a pair of cooling members disposed so as to sandwich the semiconductor modules and configured to cool the semiconductor modules; a pair of sandwiching members each disposed on an opposite side of the semiconductor module across a corresponding one of the pair of cooling members to oppose the corresponding one of the pair of cooling members; and a coupling portion that couples a pair of sandwiching members to each other and presses each of the pair of sandwiching members against the opposing one of the cooling members, in which at least one of the pair of sandwiching members includes a plurality of support portions disposed to oppose ends of the arranged semiconductor modules and a space between the semiconductor modules, and a spring portion extending from each of the plurality of support portions in an arrangement direction of the semiconductor modules and abutting the cooling member, and the coupling portion couples the support portion provided to the one of the pair of sandwiching members and another sandwiching member.

A semiconductor package includes an interposer, a redistribution layer chip, and a semiconductor element. The redistribution layer chip includes a redistribution element having a surface overlapping the semiconductor element and a first mold resin layer mounted to an opposite surface of the redistribution element and containing resin. The opposite surface is opposite the surface of the redistribution element overlapping the semiconductor element. The redistribution element includes an insulating layer having an insulation property and a first redistribution layer covered by the insulating layer. The first redistribution layer includes a first conductive portion at least partly located on the surface of the redistribution element overlapping the semiconductor element. The interposer includes a second redistribution layer including a second conductive portion located on a surface of the interposer overlapping the semiconductor element. The semiconductor element is electrically connected to the first conductive portion and the second conductive portion.

The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

A circuit board includes an electronic component and a printed wiring board to which the electronic component is mounted by soldering. The electronic component includes a pad electrode disposed at a bottom portion of a body part. The pad electrode has a leading end electrode part laterally protruding from a first side face of the body part, and an internal electrode part provided integrally with the leading end electrode part and positioned at a bottom face of the body part. The printed wiring board has, on a substrate, a first pad and a second pad provided so as to be separated from the first pad. The leading end electrode part is joined to the first pad by soldering and the internal electrode part is joined to the second pad by soldering.

A temperature sensor module includes a temperature sensor that outputs a detection signal corresponding to a temperature. The module has a mounting portion where the temperature sensor is mounted. A sealing member encapsulates the temperature sensor and the mounting portion. Additionally, the module includes a heat-conductive member that is thermally connected to the temperature sensor and made of a material with higher thermal conductivity than the sealing member. The heat-conductive member is arranged within the sealing member so that a part of the heat-conductive member is exposed from the sealing member. The heat-conductive member is designed to be in contact with a part to be measured.

A semiconductor device includes: a semiconductor element including a semiconductor layer and a first electrode disposed on one side in a thickness direction with respect to the semiconductor layer; a first conductive member bonded to the first electrode; a second conductive member bonded to the semiconductor element on the other side in the thickness direction; and a sealing resin including a first resin surface and a second resin surface respectively oriented toward the one side and the other side in the thickness direction and covering the semiconductor element and at least a portion of each of the first conductive member and the second conductive member. The first electrode includes a first metal layer that contains a metal having a higher thermal conductivity than solder.

Thermal resistance of a sintered metal joining section is reduced to cope with an increase in the area of a chip size and layer thinning of the semiconductor chip. A sintered metal layer joins the semiconductor chip to a wiring layer and the wiring layer has a trench extending from the semiconductor chip mounting region where the semiconductor chip is mounted to the outside of the semiconductor chip mounting region. The sintered metal layer is formed in the trench and to the outside of the upper end of the trench and in the trench formed to the outside of the semiconductor chip mounting region. The depth of the trench differs between the trench in the vicinity of the center of the semiconductor chip mounting region and the trench in the vicinity of the end portion of the semiconductor chip mounting region.

The invention provides an electronic cascode power device. The electronic cascode power device has a high-side terminal, a low-side terminal and a control terminal. The electronic cascode power device comprises: a high-voltage silicon (Si) super-junction MOSFET with a drain connected to the high-side terminal of the cascode device; a low-voltage gallium nitride (GaN) HEMT with a drain connected to a source of the high-voltage Si super-junction MOSFET, a source connected to the low-side terminal of the cascode device and a gate connected to the control terminal of the cascode device; and an overvoltage clamping circuit connected between the drain and source of the low-voltage GaN HEMT. The provided cascode structure can effectively suppress the reverse-recovery process of super-junction MOSFET, achieving nearly 50% reduction in overall switching loss at high current levels.