A discharge protection semiconductor structure is provided that includes a substrate, a well positioned on the substrate, a first contact diffusion and a second contact diffusion, the first contact diffusion and the second contact diffusion positioned on the top side of the well, and a resistor positioned between the first contact diffusion and a second contact diffusion.

An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.

A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region.

A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.

The short-circuit protection circuit for a Gate Driver on Array (GOA) liquid crystal panel contains a power module, a first booster module, a feedback module, and a second booster module series-connected in the this order. A control module is electrically connected to the first booster, feedback, and second booster modules. The power module provides a power voltage. The control module provides a pulse width modulation (PWM) signal so as to control the first and second booster modules to transform the power voltage into driving voltage. The feedback module extracts a feedback current from a current flowing from the first to the second booster module and provides a feedback signal to the control module. When the feedback current exceeds a current threshold, the control module cuts off the PWM signal output so as to achieve short-circuit protection. A liquid crystal panel incorporating the above short-circuit protection circuit is also provided.

Electrostatic discharge (ESD) protection devices and methods. The ESD protection devices include a semiconductor substrate, a buried semiconducting layer, and an overlying semiconducting layer. The ESD protection devices also include a first bipolar device that includes a first bipolar device region, a first device base region, and a first device emitter region. The ESD protection devices also include a second bipolar device that includes a second bipolar device region, a second device well, a second device base region, and a second device emitter region. The ESD protection devices further include a sinker well that electrically separates the first bipolar device from the second bipolar device. The ESD protection devices are configured to transition from an off state to an on state responsive to receipt of greater than a threshold ESD voltage by the first device base region. The methods include methods of forming the ESD protection device.

An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by an undoped or lightly doped ring region. The ring region is surrounded by the outer region. The device further includes a semiconductor region over the buried layer, a first well of the first conductivity type in the semiconductor region, a first transistor in the semiconductor region, and a second transistor in the semiconductor region. The first well forms a collector of the first transistor and a collector of the second transistor.

The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.