An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer on the fins. A gate electrode extending in a second direction, an electrode pattern of a capacitor, and a resistor are on the insulation layer. A drain is on a first side of the gate electrode, and a source is on a second side of the gate electrode. A connection structure electrically connects the electrode pattern, the gate electrode and the resistor. The electrode pattern is on the first side or the second side of the gate electrode, and the resistor is on the other of the first side or the second side. At least a portion of the resistor extends in the second direction.

In a semiconductor device, a control circuit controls a potential difference of a switching element between a first terminal connected to a power source node and a second terminal connected to a first reference node. A first clamping circuit is connected between the first terminal and a control terminal of the switching element and is energized by a voltage equal to or higher than a first clamp voltage. A second clamping circuit is connected between the control terminal and the first reference node and clamps the potential difference to a second clamp voltage lower than the first clamp voltage. A third clamping circuit is connected between the control terminal and the second terminal. The control unit activates the second clamping circuit when a load current is equal to or greater than a predetermined threshold voltage, and activates the third clamping circuit after a predetermined time period elapses.

An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a protection resistor coupled between the input/output transistor and the bondpad and a bootstrap clamp transistor coupled between the drain of the input/output transistor and the gate of the input/output transistor. An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a protection resistor coupled between the input/output transistor and the bondpad and a bootstrap clamp diode coupled between the drain of the input/output transistor and the gate of the input/output transistor and a biasing resistor coupled between the gate and source of the input/output transistor.

An apparatus includes a device, a comparison circuit, and a switch. The device includes a first terminal coupled to a first power supply signal, and a second terminal coupled to a ground reference. The comparison circuit is configured to compare a first voltage level on the first power supply signal to a second voltage level of a second power supply signal, and enable the device in response to a determination that the first voltage level is greater than the second voltage level. The switch circuit is configured to couple a power supply terminal of the comparison circuit to the first power supply signal in response to determining that the first voltage level is greater than the second voltage level, and to couple the power supply terminal to the second power supply signal in response to determining that the first voltage level is less than the second voltage level.

A silicon controlled rectifier, an electrostatic discharge (ESD) protection circuit including the silicon controlled rectifier and an integrated circuit including the silicon controlled rectifier or ESD protection circuit. The silicon controlled rectifier includes a first region having a first conductivity type and a second region having a second conductivity type located adjacent the first region in a semiconductor substrate. A junction is formed at a boundary between the first region and the second region. Contact regions of the first conductivity type and the second conductivity type located in each of the first region and the second region. A further contact region of the second conductivity type is located in the second region, in between the contact region of the first conductivity type and the junction. The further contact region and the contact region of the second conductivity type in the second region are connected together for biasing the second region.

The disclosure provides an ESD protection circuit. The ESD protection circuit comprises: a clamping unit, a driving unit, a resistance unit, a switch unit, and a capacitance unit. The clamping device is coupled between a first power source and a second power source. The driving unit is coupled between the clamping device and a reference node. The resistance unit is coupled between the first power source and the reference node. The switch unit is coupled to the driving unit via the reference node. The capacitance unit is coupled between the switch unit and the second power source. Under a normal operation condition, the driving unit controls the switch unit to be in an un-conducting status. Under an ESD condition, the driving unit controls the switch unit to be in a conducting status.

An active protective circuit for a measuring amplifier of an electrical impedance tomograph includes a circuit component arrangement including an electrode input and an output and a control input for a control voltage. The output is configured for connection to a measuring amplifier for an electrical impedance tomograph. The circuit component arrangement creates a conductive connection between the electrode input of the circuit component arrangement and the output of the circuit component arrangement when the applied control voltage is within a first voltage range and does not create a conductive connection when the applied control voltage is within a second voltage range. The voltage being applied to the control input is within the second voltage range when a voltage, which is within a cut-off range, is applied to the electrode input. An electrode belt for impedance tomography has the active protective circuits associated with the electrodes.

An electrostatic discharge (ESD) protection device includes a substrate including a plurality of active fins and a plurality of grooves. The ESD protection device includes an insulation layer on the active fins and the grooves, and a gate electrode on the active fins. The ESD protection device includes a first impurity region adjacent to a first side of the gate electrode, and a second impurity region adjacent to a second side of the gate electrode. The second side of the gate electrode may be arranged opposite to the first side. The ESD protection device includes an electrode pattern of a capacitor overlapping the first impurity region, a resistor overlapping the second impurity region, and a connection structure electrically connecting the electrode pattern, the gate electrode, and the resistor to each other.

ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event.

An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit.