An integrated circuit (IC) device comprises a conductive contact at a surface of the IC device. A resistive element is coupled between the conductive contact and first circuitry. Second circuitry is coupled between the resistive element and the conductive contact. The second circuitry is further coupled with a supply line and comprises at least one of a diode or a power clamp. The resistive element is disposed in a first metallization layer of the IC device. A first dielectric layer is adjacent to the first metallization layer. A second metallization layer is adjacent to the first dielectric layer. A height of the first dielectric layer and the second metallization layer is a first distance. A zone overlaps the resistive element, and extends a second distance away from the resistive element. The zone is free of conductive material and the second distance is greater than the first distance.

A discharge protection semiconductor structure is provided that includes a substrate, a well positioned on the substrate, a first contact diffusion and a second contact diffusion, the first contact diffusion and the second contact diffusion positioned on the top side of the well, and a resistor positioned between the first contact diffusion and a second contact diffusion.

The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

An integrated circuit includes a first horizontal conductor and a second horizontal conductor. The integrated circuit includes a first diode between a first first-type block and a first second-type block, a second diode between a second first-type block and a second second-type block, and a third diode between a third first-type block and a third second-type block. The first first-type block and the first second-type block are aligned along a first column. The second first-type block and the second second-type block are aligned along a second column. The third first-type block and the third second-type block are aligned along a third column. The second first-type block is connected to the first second-type block through the second horizontal conductor. The third first-type block is conductively connected to the second second-type block through the first horizontal conductor.

According to one embodiment, a display device includes first semiconductor layers crossing a first scanning line in a non-display area, the first semiconductor layers being a in number, second semiconductor layers crossing a second scanning line in the non-display area, the second semiconductor layers being b in number, and an insulating film disposed between the first and second semiconductor layers and the first and second scanning lines, wherein a and b are integers greater than or equal to 2, and a is different from b, and the first and second semiconductor layers are both entirely covered with the insulating film.

An electrostatic discharge (ESD) protection cell region (of a semiconductor device) includes a resistor-diode ladder and a power clamp circuit coupled in parallel between a first power rail PR1 and a second power rail PR2. The resistor-diode ladder is also coupled between an input/output (I/O) pad of the semiconductor device and core circuitry of the semiconductor device. The resistor-diode ladder includes: a first diode coupled between a first node and the first power rail; a first resistor coupled between the first node and a second node; a second diode coupled between the second node and the first power rail; a third diode coupled between the first node and the second power rail; and a fourth diode coupled between the second node and the second power rail. The first node is coupled to the I/O pad. The resistor-diode ladder is coupled between the I/O pad and the core circuitry.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes: a substrate (120); a first nitride semiconductor layer (130) on the substrate (120); a second nitride semiconductor layer (140) on the first nitride semiconductor layer (130) and having a band gap greater than a band gap of the first semiconductor layer (130); a transistor (14) on the second nitride semiconductor layer (140); and a protection circuit (40) on the second nitride semiconductor layer (140), wherein the protection circuit (40) is configured to dispel electrons from a gate node of the transistor (14) when a voltage on the gate node exceeds a first threshold voltage.

The present disclosure discloses an array substrate and a method of preparing the array substrate. The method comprises providing a substrate having a display area thereon and forming a plurality of pixel structures in said display area. At least one of the plurality of pixel structures is prepared through the following procedures: forming successively, on the substrate, a patterned first metal layer which has a gate line and a floating metal pattern that is insulative to the gate line, a gate insulation layer, and a patterned second metal layer which has a data line, a source, and a drain, wherein the data line is arranged in correspondence with the floating metal pattern and spaced from the floating metal pattern through the gate insulation layer. The array substrate of the present disclosure can increase capacitance for storage of the static electricity generated in a dry plasma bombardment of the second metal layer, thus preventing electrostatic breakdown caused by insufficient capacitive storage.

Fabrication of a wireless device involves providing a packaging substrate configured to receive a plurality of components, mounting a radio-frequency module on the packaging substrate, the radio-frequency module including a power amplifier including a bipolar transistor having collector, emitter, base and sub-collector regions, the radio-frequency module further including a conductive via positioned within 35 m of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level, and electrically connecting the radio-frequency module to the packaging substrate using a plurality of connectors.

In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device.