A bipolar solar cell includes a backside junction formed by an N-type silicon substrate and a P-type polysilicon emitter formed on the backside of the solar cell. An antireflection layer may be formed on a textured front surface of the silicon substrate. A negative polarity metal contact on the front side of the solar cell makes an electrical connection to the substrate, while a positive polarity metal contact on the backside of the solar cell makes an electrical connection to the polysilicon emitter. An external electrical circuit may be connected to the negative and positive metal contacts to be powered by the solar cell. The positive polarity metal contact may form an infrared reflecting layer with an underlying dielectric layer for increased solar radiation collection.

An ultrathin silicon oxynitride interface material, a tunnel oxide passivated structure and preparation methods and applications thereof are provided. The ultrathin silicon oxynitride interface material is an SiON film with a thickness of 1 nm to 4 nm, and the percentage content of N atoms is 1% to 40%. Compared with silicon oxide, the diffusion rate of boron in the SiON film of the present disclosure is low, which effectively reduces the damaging effect of boron, improves the integrity of the SiON film and maintains the chemical passivation effect. The SiON film with high nitrogen concentration can noticeably lower the concentration of boron on the silicon surface so as to lessen the boron-induced defects. Furthermore, the SiON film has an energy band structure approximate to silicon nitride, which increases the hole transport efficiency and hole selectivity, and further improves the passivation quality and reduces the contact resistivity.

A solar cell and a manufacturing method thereof, and a photovoltaic system. The solar cell includes: a substrate layer including a first surface and a second surface arranged oppositely along a thickness direction thereof; a tunnel oxide layer, a first doped polysilicon layer, and a first passivation layer sequentially arranged on the first surface of the substrate layer in a direction gradually away from the substrate layer; and a first finger electrode layer, at least one of the first fingers being arranged in first connection holes, bottoms of the first connection holes being located in the first doped polysilicon layer, and the first fingers passing through the first connection holes corresponding thereto to be electrically connected to the first doped polysilicon layer; and in the first direction, widths of the first connection holes being all less than widths of the first fingers corresponding to the first connection holes. While ensuring good electrical connection, the solar cell causes less damage and recombination to a passivation structure of the solar cell, and has high photoelectric conversion efficiency.

A semiconductor device includes a semiconductor stack, a reflective structure, and a conductive structure. The semiconductor stack includes a first semiconductor structure, a second semiconductor structure and an active region located between the first semiconductor structure and the second semiconductor structure. The reflective structure is located at a side of semiconductor stack closed to the first semiconductor structure, and includes a first metal. The conductive structure locates between the reflective structure and the first semiconductor structure, and includes a first region overlapping with the active structure and a second region which does not overlap with the active structure. The first metal in the second region has a concentration smaller than 5 atomic percent.

The present disclosure provides a double-sided passivated contact cell, where a front side and a rear side of the double-sided passivated contact cell each are provided with a tunnel layer, a doped polysilicon layer, and a passivation layer sequentially from an inside to an outside; and for the doped polysilicon layer at the front side and the doped polysilicon layer at the rear side, one of the doped polysilicon layer at the front side and the doped polysilicon layer at the rear side is a boron and carbon co-doped polysilicon layer, and the other of the doped polysilicon layer at the front side and the doped polysilicon layer at the rear side is a phosphorus and carbon co-doped polysilicon layer. The present disclosure further provides a preparation method of the double-sided passivated contact cell.

A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.

The present inventive concept relates to an RGB micro-light-emitting diode having a vertically-stacked structure with corner mesa contact structures, and a manufacturing method thereof. The RGB micro-light-emitting diode having a vertically-stacked structure with corner mesa contact structures includes an n-type contact electrode layer, a first light-emitting structure, a common electrode layer, a second light-emitting structure, a tunnel junction layer, and a third light-emitting structure, which are sequentially stacked on a substrate. The RGB micro-light-emitting diode with a reduced unit area can be easily manufactured by forming the corner mesa contact structure on each of the n-type contact electrode layers by etching the vertically-stacked structure, forming contact structures on the n-type contact electrode layers, followed by electrical connection.

A solar cell structure comprises a substrate including a front side and a back side. A first tunnel oxide layer, a first polycrystalline silicon layer, a first silicon nitride layer, and a plurality of first electrodes are sequentially formed on the front side of the substrate. A second tunnel oxide layer, a second polycrystalline silicon layer, a second silicon nitride layer, and a plurality of second electrodes are sequentially formed on the back side of the substrate.

A passivation process, including the following successive steps: a) providing a structure including a crystalline silicon-based substrate having opposite first and second surfaces; first and second oxide films; b) applying ultraviolet radiation to the structure, under an ozone atmosphere, in such a way that the first oxide film has: a thickness strictly greater than the thickness of the second oxide film, and/or a composition closer to the stoichiometric compound; c) forming first and second polysilicon layers on the first and second oxide films, respectively, these first and second polysilicon layers comprising phosphorus atoms and boron atoms, respectively; d) applying a heat treatment at a temperature greater than or equal to the electrical activation temperature of the boron atoms so as to electrically activate the phosphorus atoms and the boron atoms concomitantly.

In a thin film photoelectric conversion device fabricated by addition of a catalyst element with the use of a solid phase growth method, defects such as a short circuit or leakage of current are suppressed. A catalyst material which promotes crystallization of silicon is selectively added to a second silicon semiconductor layer formed over a first silicon semiconductor layer having one conductivity type, the second silicon semiconductor layer is partly crystallized by a heat treatment, a third silicon semiconductor layer having a conductivity type opposite to the one conductivity type is stacked, and element isolation is performed at a region in the second silicon semiconductor layer to which a catalyst material is not added, so that a left catalyst material is prevented from being diffused again, and defects such as a short circuit or leakage of current are suppressed.