Method of making a current collecting grid for solar cells, including the steps of a) providing a continuous layer stack (1) on a substrate (8), the layer stack (1) including an upper (2) and a lower (3) conductive layer having a photoactive layer (4) interposed there between; b) selectively removing the upper conductive layer (2) and the photoactive layer (4) for obtaining a first contact hole (10) extending through the upper conductive layer (2) and photoactive layer (4) exposing the lower conductive layer (3); c) printing a front contact body (4) on the upper conductive layer (2) and a back contact body (5) in the first contact hole (10) on the lower conductive layer (3) and forming an electrically insulating first gap surrounding the back contact body (5) between the upper conductive layer (2) and the back contact body (2).

Method of manufacturing a single-side-contacted photovoltaic device (1), comprising the steps of: a) providing a photovoltaically-active substrate (3) defining a plurality of alternating hole collecting zones (3a) and electron collecting zones (3b) arranged in parallel strips; b) depositing a conductive layer (5) across said zones; c) depositing at least one conductive track (9) extending along at least part of each of said zones (3a, 3b); d) selectively forming a dielectric layer (7) on each of said zones (3a, 3b), so as to leave an exposed area free of dielectric at an interface between adjacent zones (3a, 3b); e) etching said conductive layer (5) in said exposed areas; f) applying a plurality of interconnecting conductors (11a, 11b) so as to electrically interconnect at least a portion of said hole collecting zones (3a) with each other, and to electrically interconnect at least a portion of said electron collecting zones (3b) with each other.

A method of forming an integrated circuit includes placing a first and a second standard cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height. Placing the first standard cell layout design includes placing a first set of pin layout patterns on a first layout level over a first set of gridlines, extending in a first direction, and having a first width in a second direction. Placing the second standard cell layout design includes placing a second set of pin layout patterns on the first layout level over a second set of gridlines, extending in the first direction, and having a second width in the second direction.

A method of forming an integrated circuit includes placing a first and a second standard cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height. Placing the first standard cell layout design includes placing a first set of pin layout patterns on a first layout level over a first set of gridlines, extending in a first direction, and having a first width in a second direction. Placing the second standard cell layout design includes placing a second set of pin layout patterns on the first layout level over a second set of gridlines, extending in the first direction, and having a second width in the second direction.

Embodiments provide a transparent electrode having high stability, low sheet resistance, and high light transmissivity, a method for producing the transparent electrode, and an electronic device using the transparent electrode.

A transparent electrode including a structure including a transparent base material, a metal grid, metal nanowire, and a neutral polythiophene mixture. The metal grid has an embedded portion embedded in the transparent base material and a protrusion portion protruding from the transparent base material, and the metal nanowire and the neutral polythiophene mixture are arranged in contact with the transparent base material or the protrusion portion.

The present invention relates to a method for laminating solar cell modules comprising a plurality of solar cells electrically connected in series. The method comprises: providing a first and a second flexible substrate portion suitable for roll-to-roll deposition; providing a plurality of first electronic conductors on said first substrate portion and a plurality of second electrodes on said second substrate portion, wherein said plurality of first and second electrodes are provided as stripes spatially separated such that a plurality of gaps is formed; depositing an electronic conductor on one end of the first and second electrodes and depositing a continuous or discontinuous active layer on said plurality of first electrodes or said plurality of second electrodes, wherein said continuous or discontinuous active layer is an organic active layer; laminating by means of heat and pressure said first and said second substrate portions together in a roll-to-roll process such that the electronic conductors are brought into physical contact with the respective electronic conductor arranged on the opposite substrate, and that the active layer is brought into physical contact with the other one of said plurality first electrodes or said plurality of second electrodes and such that the active layer is brought into electrical contact with said plurality of first electrodes and said plurality of second electrodes. The plurality of first electrodes is arranged off-set relative said plurality of second electrodes such that each of said plurality of gaps between said plurality of second electrodes are partly or fully covered at least in one direction by respective one of said plurality of first electrodes. The present invention also relates to a solar cell module.

An ultra-thin shadow mask comprises a plastic foil including a plurality of apertures, wherein the ultra-thin shadow mask is less than 25 μm thick, and wherein the ultra-thin shadow mask has a feature size of at least 1 μm to about 100 μm. An organic photovoltaic (OPV) device comprises a first electrode including a first grid structure, the first grid structure having a feature size of at least 1 μm to about 100 μm, a heterojunction under the first electrode, a second electrode under the heterojunction including a second grid structure, and a plurality of outcoupling layers over the first electrode. Related methods are also disclosed.

The present invention relates to a working electrode (1a) for a photovoltaic device, comprising a light absorbing layer (3) and a conductive layer (6) arranged in electrical contact with the light absorbing layer (3), and the light absorbing layer (3) comprises a light absorbing photovoltaic material consisting of a plurality of dye molecules. The light absorbing layer (3) is formed by a layer of a plurality of clusters (7), whereby each cluster (7) is formed by dye molecules and each dye molecule in the cluster (7) is bonded to its adjacent dye molecules.

An optoelectronic component, including: a bottom electrode, a top electrode, a layer system having at least one photoactive layer, the layer system being disposed between the bottom electrode and the top electrode, a planarization layer disposed on a side of the bottom electrode and/or top electrode facing away from the layer system, at least one barrier layer disposed on the planarization layer, and at least one busbar, the at least one busbar being disposed on the at least one barrier layer, wherein: the planarization layer has electrically conductive particles the electrically conductive particles being introduced into the planarization layer, and the electrically conductive particles electrically conductively bridge the planarization layer through the at least one barrier layer such that the bottom electrode and/or the top electrode electrically conductively contacts the at least one busbar.

Photovoltaic devices, and methods of fabricating photovoltaic devices. The photovoltaic devices may include a first electrode, at least one quantum dot layer, at least one semiconductor layer, and a second electrode. The first electrode may include a layer including Cr and one or more silver contacts.