[Problem] To provide a phononic material that exhibits a voltage-current characteristic to make current flow even when there is no potential gradient, and a method for producing the same. [Solution] A phononic material 1 has a periodic structure body 2′ in which structures 3 are periodically and regularly disposed in a constituent 2, and the periodic structure body 2′ exhibits a voltage-current characteristic to make current flow even when a potential gradient is 0 V. A method for producing the phononic material 1 has such an outline as to carry out a heat treatment to cool and warm the periodic structure body after applying a current with a magnitude to make an electrical resistance characteristic disappear to the periodic structure body 2′ having the electrical resistance characteristic that exhibits an electrical resistance value of 0Ω or less.

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

Conventional readout of a superconducting nanowire single-photon detector (SNSPD) sets an upper bound on the output voltage to be the product of the bias current and the load impedance, I.sub.B×Z.sub.load, where Z.sub.load is limited to 50Ω in standard RF electronics. This limit is broken/exceeded by interfacing the 50Ω load and the SNSPD using an integrated superconducting transmission line taper. The taper is a transformer that effectively loads the SNSPD with high impedance without latching. The taper increases the amplitude of the detector output while preserving the fast rising edge. Using a taper with a starting width of 500 nm, a 3.6× higher pulse amplitude, 3.7× faster slew rate, and 25.1 ps smaller timing jitter was observed. The taper also makes the detector's output voltage sensitive to the number of photon-induced hotspots and enables photon number resolution.

An electronic device includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material includes a first wire and a loop that is (1) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state.

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

A reinforced thin-film device (100, 200, 500) including a substrate (101) having a top surface for supporting an epilayer; a mask layer (103) patterned with a plurality of nanosize cavities (102, 102′) disposed on said substrate (101) to form a needle pad; a thin-film (105) of lattice-mismatched semiconductor disposed on said mask layer (103), wherein said thin-film (105) comprises a plurality of in parallel spaced semiconductor needles (104, 204) of said lattice-mismatched semiconductor embedded in said thin-film (105), wherein said plurality of semiconductor needles (104, 204) are substantially vertically disposed in the axial direction toward said substrate (101) in said plurality of nanosize cavities (102, 102′) of said mask layer (103), and where a lattice-mismatched semiconductor epilayer (106) is provided on said thin-film supported thereby.