A memristor material is disclosed which has the chemical formula R.sub.1-xA.sub.xB0.sub.3, wherein R is one of Eu, Gd, Tb, Nd, A is one of Ca, Sr, Ba, B is one of Mn, Co, Ni, and x is larger than 0 but smaller than 1, a preferred example being Gd.sub.1-xCa.sub.xMn0.sub.3 (GCMO) with x not less than 0.2 to obtain practical resistance switching ratios. A memristor can be manufactured by pulsed laser deposition using a sintered target of said material.

Provided is a three-dimensional vertical memory device including: a semiconductor substrate, a vertical columnar channel region provided on the semiconductor substrate and having a void of a predetermined size therein; a source electrode and a drain electrode spaced apart from each other with the channel region interposed therebetween; and a gate stack formed on the channel region.

A plurality of memory cells in a 3D cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.

A phase change resistive memory includes an upper electrode; a lower electrode; a layer made of an active material, called an active layer; the memory passing from a highly resistive state to a weakly resistive state by application of a voltage or a current between the upper electrode and the lower electrode and wherein the material of the active layer is a ternary composed of germanium Ge, tellurium Te and antimony Sb, the ternary including between 60 and 66% of antimony Sb.

Switching oxide engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. A method for fabricating a crossbar device may include forming a bottom electrode on a substrate, forming a switching oxide stack on the bottom electrode, and forming a top electrode on the switching oxide stack. Fabricating the switching oxide stack may include fabricating a plurality of base oxide layers and a plurality of discontinuous oxide layers alternately stacked, wherein the base oxide layers comprise one or more base oxides, wherein the one or more base oxides comprise at least one of TaOx, HfOx, TiOx, or ZrOx.

An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.

Disclosed is a method of fabricating a resistive switching memory. A method of fabricating a resistive switching memory according to an embodiment of the present invention includes a step of forming a lower electrode on a substrate; a step of forming a resistive switching layer on the lower electrode using sputtering; and a step of forming an upper electrode on the resistive switching layer, wherein, in the step of forming a resistive switching layer on the lower electrode using sputtering, the substrate is disposed in a region, which is not reached by plasma generated by the first and second targets, between the first target and the second target disposed above the substrate to deposit the resistive switching layer.

A selective non-volatile memory device includes a first electrode, a second electrode and at least one layer made of an active material. The device has at least two programmable memory states associated with two voltage thresholds and also provides a selective role when it is in a highly resistive state.

Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.

A ReRAM device includes a dielectric layer, a bottom electrode, a data storage layer, a metal covering layer, and a top electrode. The dielectric layer has a recess. At least a portion of the bottom electrode is exposed through the recess. The data storage layer is disposed on a sidewall and a bottom surface of the recess, electrically contacts with the bottom electrode, and has a top portion lower than an opening of the recess. The metal covering layer blanket covers the data storage layer, has an extension portion covering the top portion, and connects to the sidewall of the recess. The top electrode is disposed in the recess, and is electrically contact with the metal covering layer.