An electrical device comprising a reconfigurable integrated circuit that includes paired top electrodes and bottom electrodes separated from each other by an active layer.

Memristors, including memristors comprising a Schottky barrier, and related systems and methods are generally described.

Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

In a semiconductor device, a device structure is positioned over a substrate, where the device structure includes devices. A wiring structure of the semiconductor device is positioned over the substrate and coupled to at least one of the devices. The wiring structure includes at least one of programmable lines and programmable vertical interconnects, where the programmable lines extend along a top surface of the substrate and the programmable vertical interconnects extend along a vertical direction perpendicular to the top surface of the substrate. The programmable lines and the programmable vertical interconnects include a programmable material having a modifiable resistivity in that the programmable lines and the programmable vertical interconnects change between being conductive and being non-conductive in responsive to a current pattern delivered to the programmable lines and the programmable vertical interconnects.

Proposed are a layered Group III-V compound having ferroelectric properties, a Group III-V compound nanosheet that may be prepared using the same, and an electrical device including the materials. Proposed is a layered compound represented by [Formula 1] M.sub.x−mA.sub.yB.sub.z (M is at least one of Group I or Group II elements, A is at least one of Group III elements, B is at least one of Group V elements, x, y, and z are positive numbers which are determined according to stoichiometric ratios to ensure charge balance when m is 0, and 0<m<x), and having ferroelectric-like properties.

Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, Sb—Te, Ge—Sb and Ge—Sb—Te thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR.sup.1R.sup.2R.sup.3).sub.3 are preferably used, wherein R.sup.1, R.sup.2, and R.sup.3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.

Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits incorporating synstors are capable of performing signal processing and learning concurrently in parallel analog mode with speed, energy efficiency, and functions superior to computers.

Proposed are a layered compound having indium and phosphide, a nanosheet that may be prepared using the same, and an electrical device including the materials. Proposed is a layered compound represented by K.sub.1-xIn.sub.yP.sub.z (0≤x≤1.0, 0.75≤y≤1.25, 1.25≤z≤1.75).

A memory cell includes a bottom electrode, a first dielectric layer, a variable resistance layer, and a top electrode. The first dielectric layer laterally surrounds the bottom electrode. A top surface of the bottom electrode is located at a level height lower than that of a top surface of the first dielectric layer. The variable resistance layer is disposed on the bottom electrode and the first dielectric layer. The variable resistance layer contacts the top surface of the bottom electrode and the top surface of the first dielectric layer. The top electrode is disposed on the variable resistance layer.