ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE

Abstract

The present disclosure provides an array substrate, a method of manufacturing the same, a display panel and a display device. The array substrate comprises a plurality of gate lines and a plurality of data lines arranged to cross with each other and define a plurality of pixel areas, each of the pixel areas comprising a thin film transistor. The array substrate further comprises a first insulating layer arranged above the thin film transistors and the data lines; a metal layer arranged above the first insulating layer; a second insulating layer arranged above the metal layer; and a pixel electrode and a common electrode arranged above the second insulating layer, between which a third insulating layer is provided. The common electrode in each of the pixel areas at least comprises two slits and the metal layer overlies the data lines.

Claims

1. An array substrate comprising: a plurality of gate lines and a plurality of data lines arranged to cross with each other and define a plurality of pixel areas, each of the pixel areas comprising a thin film transistor, a first insulating layer arranged above the thin film transistors and the data lines, a metal layer arranged above the first insulating layer, a second insulating layer arranged above the metal layer, and a pixel electrode and a common electrode arranged above the second insulating layer, between which a third insulating layer is provided, wherein, the common electrode in each of the pixel areas at least comprises two slits, the metal layer overlies the data lines, the pixel electrode is electrically connected to a first terminal of the thin film transistor via a via hole at least penetrating the first insulating layer and the second insulating layer, and the first terminal is a source or a drain.

2. The array substrate according to claim 1, wherein the metal layer is electrically connected to the common electrode via a via hole penetrating the second insulating layer and the third insulating layer.

3. The array substrate according to claim 1, wherein the metal layer comprises any one or more of molybdenum, copper, and aluminum.

4. The array substrate according to claim 1, wherein a width of the metal layer is larger than a width of the data line, and a center of the width of the metal layer and a center of the width of the data line are located on a same straight line.

5. The array substrate according to claim 4, wherein the width of the metal layer is 3 to 4 μm.

6. The array substrate according to claim 1, wherein a distance between an edge of the metal layer and an edge of the data line is 0.8 to 1.5 μm.

7. The array substrate according to claim 1, wherein a distance between adjacent data lines is not greater than 14 μm.

8. A display panel comprising: a color substrate and the array substrate according to claim 1 arranged opposite to each other.

9. A display device comprising the display panel according to claim 8.

10. A method of manufacturing an array substrate comprising: forming a pattern comprising a first terminal, a second terminal and data lines, the first terminal and the second terminal being one of a source and a drain, respectively; forming a first insulating layer above the data lines; forming a metal layer, the metal layer being located above the first insulating layer and overlying the data lines; forming a second insulating layer above the metal layer, and forming a via hole at least penetrating the first insulating layer and the second insulating layer; forming a pixel electrode, the pixel electrode being located above the second insulating layer, and the pixel electrode being electrically connected to the first terminal via the via hole at least penetrating the first insulating layer and the second insulating layer; forming a third insulating layer above the pixel electrode; forming a common electrode, the common electrode being located above the third insulating layer and at least comprising two slits.

11. The method according to claim 10, further comprising: forming a via hole at least penetrating the second insulating layer and the third insulating layer, the metal layer being electrically connected to the common electrode via the via hole at least penetrating the second insulating layer and the third insulating layer.

12. The method according to claim 10, prior to the step of forming a pattern comprising a first terminal, a second terminal and data lines, further comprising: forming a gate on a base substrate; depositing a gate insulating layer on the gate; forming an active layer on the gate insulating layer.

13. The method according to claim 11, prior to the step of forming a pattern comprising a first terminal, a second terminal and data lines, further comprising: forming a gate on a base substrate; depositing a gate insulating layer on the gate; forming an active layer on the gate insulating layer.

14. The display panel according to claim 8, wherein the metal layer is electrically connected to the common electrode via a via hole penetrating the second insulating layer and the third insulating layer.

15. The display panel according to claim 8, wherein the metal layer comprises any one or more of molybdenum, copper, and aluminum.

16. The display panel according to claim 8, wherein a width of the metal layer is larger than a width of the data line, and a center of the width of the metal layer and a center of the width of the data line are located on a same straight line.

17. The display panel according to claim 16, wherein the width of the metal layer is 3 to 4 μm.

18. The display panel according to claim 8, wherein a distance between an edge of the metal layer and an edge of the data line is 0.8 to 1.5 μm.

19. The display panel according to claim 8, wherein a distance between adjacent data lines is not greater than 14 μm.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0030] The drawings described herein serve to provide a further understanding of the present disclosure and form part of the present disclosure. The illustrative embodiments of the present disclosure and their description serve to explain the present disclosure and do not limit the present disclosure in an inappropriate manner. In the drawings:

[0031] FIG. 1 is a schematic diagram of an array substrate in the prior art;

[0032] FIG. 2 is a schematic diagram of an array substrate having a PCI structure in the prior art;

[0033] FIG. 3 is a schematic sectional diagram of an array substrate according to embodiments of the present disclosure;

[0034] FIG. 4 is a schematic diagram of a flow for carrying out a method of manufacturing an array substrate according to embodiments of the present disclosure;

[0035] FIGS. 5a-5j are schematic diagrams in the process of manufacturing an array substrate according to embodiments of the present disclosure.

DETAILED DESCRIPTION

[0036] In an Advanced Super Dimension Switch (ADS) mode, two layers of transparent electrodes (made of indium tin oxide ITO) are formed on an array substrate. Usually, one layer of the ITO electrodes is used as a common electrode (Vcom), while the other is used as a pixel electrode (Vpixel). In a conventional structure, the pixel electrode is usually located above the common electrode, as shown in FIG. 1. In this structure, the common electrode is a structure without slit. Since in the structure without slit, a pixel is interfered with by the electric field of a pixel next to it, color mixing is liable to take place. In order to solve this problem, the prior art proposes a pixel inversion (PCI) structure, i.e. the common electrode is located above the pixel electrode as shown in FIG. 2. However, in the PCI structure, since line-by-line scanning is performed on the gate lines, all the data lines would be turned on when each row of gate line is being scanned. In order to prevent the liquid crystal molecules from being deflected by the electric field formed due to the turn-on of the data lines, a light-shielding portion (a portion between edges of the common electrode and the gate line/data line (S/D)) is formed by means of the common electrode, the width of which needs to be no less than 3 μm. In this way, at most one slit can be formed between the common electrodes, which decreases the liquid crystal efficiency such that the driving voltage is increased.

[0037] In order to avoid the problem of color mixing resulting from the interaction between adjacent pixels, embodiments of the present invention provide an array substrate, a method of manufacturing the same, a display panel, and a display device.

[0038] Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings. It is to be understood that the exemplary embodiments described herein are only for the purpose of illustrating and explaining the present disclosure, rather than limiting the present disclosure, and that embodiments of the present disclosure and features therein may be combined with each other without causing conflict.

[0039] An array substrate provided by an embodiment of the present disclosure comprises a plurality of gate lines and a plurality of data lines arranged to cross with each other and define a plurality of pixel areas, each of the pixel areas comprising a thin film transistor.

[0040] As shown in FIG. 3, the array substrate further comprises a first insulating layer 31 arranged above the thin film transistor and the data lines; a metal layer 32 arranged above the first insulating layer; a second insulating layer 33 arranged above the metal layer 32; and a pixel electrode 34 and a common electrode 35 arranged above the second insulating layer. A third insulating layer 36 is provided between the pixel electrode 34 and the common electrode 35, and the common electrode 35 in each pixel area at least comprises two slits. Upon specific implementation, the metal layer 32 overlies the data lines, and the pixel electrode 34 is electrically connected to the drain of the thin film transistor via a via hole penetrating the first insulating layer 31 and the second insulating layer 33.

[0041] It is to be noted that, although in the above embodiment the pixel electrode 34 is electrically connected to the drain of the thin film transistor via a via hole penetrating the first insulating layer 31 and the second insulating layer 33, in an alternative embodiment, the pixel electrode 34 is electrically connected to the source of the thin film transistor via a via hole penetrating the first insulating layer 31 and the second insulating layer 33.

[0042] Upon specific implementation, the metal layer 32 may be electrically connected to the common electrode 35 via a via hole penetrating the second insulating layer 33 and the third insulating layer 36.

[0043] Upon specific implementation, the metal layer 32 may employ a metal having small resistance or an alloy of several metals, which is not limited in embodiments of the present disclosure. For example, the metal layer may employ one or more of the metals: molybdenum, copper, aluminum, and the like. It is to be noted that when the metal layer employs a low reflective metal such as molybdenum, it can actually act as a black matrix (BM) (i.e. light-shielding portion) since the metal blocks light. On such basis, in embodiments of the present disclosure, the width of BM of the color substrate can be reduced or a color substrate without BM can be used.

[0044] Upon specific implementation, the center of the width of the metal layer is located on the same straight line as the center of the width of the data line, and the distance between the edge of the metal layer and the edge of the data line is, for example, 0.8 to 1.5 μm. When the width of the data line is 2 μm, the width of the metal layer can be formed into about 3 to 4 μm.

[0045] It is to be noted that the array substrate provided by embodiments of the present disclosure is particularly applicable to the case of ultra-high resolution (600 to 800 PPI), that is, the distance between adjacent data lines is not greater than 14 μm.

[0046] Upon specific implementation, the above array substrate may further comprise a glass substrate 41, a gate 42, a gate insulating layer 43 and an active layer 44, as shown in FIG. 5i, wherein the gate 42 is located on the glass substrate 41, the gate insulating layer 43 is located above the gate 42, and the active layer 44 is located above the gate insulating layer. The data lines are provided in the same layer as the source/drain (S/D), and the gate lines are provided in the same layer as the gate 42. The first insulating layer 31 is arranged above the gate lines and the data lines, the metal layer 32 is arranged above the first insulating layer 31, the second insulating layer 33 is arranged above the metal layer 32, the pixel electrode 34 and the common electrode 35 (not shown) are arranged above the second insulating layer 33, and a third insulating layer 36 is provided between the pixel electrode 34 and the common electrode 35.

[0047] The array substrate provided by embodiments of the present disclosure is further added with a second insulating layer as compared to the array substrate using a PCI structure. Upon specific implementation, when the first insulating layer is formed, the thickness thereof may be half the thickness of that in the existing PCI structure or less.

[0048] In embodiments of the present disclosure, the function of the light-shielding portion in the conventional PCI structure is realized by the metal layer so that there is no need to take into account the distance between edges of the common electrode and the data line when the common electrode is being formed, thereby a plurality of slits can be formed as practically required. Consequently, the liquid crystal efficiency can be increased and the driving voltage can be decreased while avoiding the problem of color mixing resulting from the interaction between adjacent pixels.

[0049] On the basis of the same inventive concept, embodiments of the present disclosure further provide a method of manufacturing an array substrate, a display panel, and a display device. Since the principles of the above method and device for solving the problem are similar to those of the above array substrate, the implementations thereof may refer to the implementation of the array substrate, and are not further described.

[0050] As shown in FIG. 4 which is a schematic diagram of a flow for carrying out the method of manufacturing an array substrate as provided by embodiments of the present disclosure, the method may comprise the steps below.

[0051] At S41, a gate metal thin film is deposited on a glass substrate, and gate lines and a gate are formed by patterning process.

[0052] Upon specific implementation, a schematic diagram of the structure of the glass substrate after the treatment of step S41 is shown in FIG. 5a. It is to be noted that FIG. 5a is a cross-sectional view of the glass substrate in which gate lines are not shown.

[0053] At S42, a gate insulating layer is deposited on the glass substrate where step S41 is completed.

[0054] Upon specific implementation, a schematic diagram of the structure of the glass substrate after the treatment of step S42 is shown in FIG. 5b.

[0055] At S43, a semiconductor thin film is deposited on the gate insulating layer, and an active layer is formed by patterning process.

[0056] Upon specific implementation, a schematic diagram of the structure of the glass substrate after the treatment of step S43 is shown in FIG. 5c. During specific implementation, in order to reduce the contact resistance between the active layer and the source/drain, the active layer may be a two-layer structure. Specifically, a doped semiconductor thin film is deposited on the gate insulating layer, and an ohmic contact layer between the active layer and the source as well as the drain is formed by patterning process to improve the performance of the TFT. For example, in the case of making an active layer using an amorphous silicon semiconductor layer material, a nitrogen ion-doped amorphous silicon layer (N+a-Si) may be made between the active layer and the source as well as the drain.

[0057] Upon specific implementation, the active layer may also be a metal oxide semiconductor such as indium gallium zinc oxide (IZGO).

[0058] At S44, a source/drain metal film is deposited on the glass substrate where step S43 is completed, and a source/drain electrode and data lines (S/D) are formed by patterning process.

[0059] Upon specific implementation, a schematic diagram of the structure of the glass substrate after the treatment of step S44 is shown in FIG. 5d.

[0060] At S45, a pattern of the first insulating layer is formed by patterning process on the glass substrate where step S44 is completed.

[0061] Upon specific implementation, a schematic diagram of the structure of the glass substrate after the treatment of step S45 is shown in FIG. 5e.

[0062] At S46, a metal layer is formed above the first insulating layer.

[0063] The metal layer is located above the first insulating layer and overlies the data lines. Upon specific implementation, a schematic diagram of the structure of the glass substrate after the treatment of step S46 is shown in FIG. 5f.

[0064] At S47, a pattern of the second insulating layer is formed by patterning process on the glass substrate where step S46 is completed, and a via hole at least penetrating the first insulating layer and the second insulating layer is formed.

[0065] Upon specific implementation, a schematic diagram of the structure of the glass substrate after the treatment of step S47 is shown in FIG. 5g.

[0066] At S48, a pixel electrode is formed on the glass substrate where step S47 is completed.

[0067] The pixel electrode is located above the second insulating layer and is electrically connected to the drain via a via hole at least penetrating the first insulating layer and the second insulating layer. Upon specific implementation, a schematic diagram of the structure of the glass substrate after the treatment of step S48 is shown in FIG. 5h.

[0068] Upon specific implementation, the pixel electrode may be an indium tin oxide (ITO) or an indium zinc oxide (IZO).

[0069] At S49, a third insulating layer is formed on the glass substrate where step S48 is completed, and a via hole at least penetrating the third insulating layer and the second insulating layer is formed.

[0070] The metal layer is electrically connected to the common electrode via the via hole at least penetrating the second insulating layer and the third insulating layer. Upon specific implementation, a schematic diagram of the structure of the glass substrate after the treatment of step S49 is shown in FIG. 5i.

[0071] At S410, a common electrode is formed on the third insulating layer and at least comprises two slits.

[0072] The common electrode is located above the third insulating layer.

[0073] Upon specific implementation, a schematic diagram of the structure of the glass substrate after the treatment of step S410 is shown in FIG. 5j.

[0074] It is to be noted that the flow shown in FIG. 4 is a flow chart for manufacturing an array substrate of a bottom gate structure. Upon specific implementation, the array substrate may also be a top gate structure. During the process of manufacturing an array substrate of a top gate structure, the gate is located above the active layer.

[0075] Upon specific implementation, the common electrode may employ an indium tin oxide (ITO) or indium zinc oxide (IZO), and so on.

[0076] Embodiments of the present disclosure further provide a display panel comprising the array substrate described above and a color substrate, wherein the array substrate and the color substrate are arranged in cell alignment and a liquid crystal is filled therebetween.

[0077] Particularly, if the metal layer in the array substrate provided in embodiments of the present disclosure is implemented using a low reflective metal such as molybdenum, the color substrate included in the display panel provided by embodiments of the present disclosure may employ a color substrate without BM or a color substrate whose BM width is reduced.

[0078] Embodiments of the present disclosure further provide a display device comprising the above display panel.

[0079] Although exemplary embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, may make other variations and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including exemplary embodiments and all variations and modifications that fall within the scope of the present disclosure.

[0080] Apparently, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope thereof. In this way, if these modifications and variations to the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies thereof, the present disclosure also intends to encompass these modifications and variations.