ELECTRONIC SECURITY COMPONENT

Abstract

An electronic component is formed on and in a semiconductor substrate. The component includes source and drain regions and a gate region between the source and drain regions. Two dielectric lateral spacing regions are provided on the semiconductor substrate against sides of the gate region. An electrical connection, formed by a silicide on a surface of at least one of said dielectric lateral spacing region, is configured to electrically connect the gate region to at least one of the source region and the drain region.

Claims

1. A method for manufacturing an electronic component which includes source and drain regions, a gate region between the source and drain regions, and a dielectric lateral spacing region against a side of said gate region, the method comprising: implanting ions in said dielectric lateral spacing region; depositing a metal layer on the surface of said dielectric lateral spacing region as well as on the gate region and at least one of the source and drain regions; applying a first heating to make the metal layer react with the gate region, said at least one of the source and drain regions, and the implanted ions in said dielectric lateral spacing region to form a silicide electrical connection extending over said dielectric lateral spacing region and configured to electrically connect the gate region to at least one of the source region and the drain region; removing unreacted portions of said metal layer after the first heating; and applying a second heating after removing the unreacted portions of said metal layer; wherein said second heating is performed at a second temperature higher than a first temperature used for the first heating.

2. The method according to claim 1, wherein the first temperature is of the order of 300° C.

3. The method according to claim 2, wherein the second temperature is of the order of 400° C.

4. The method according to claim 1, wherein implanting comprises implanting an ion dose of that does not exceed 5×10.sup.13 ions/cm.sup.2.

5. The method according to claim 1, wherein implanting comprises implanting an ion dose that does not exceed 2×10.sup.14 ions/cm.sup.2.

6. The method according to claim 1, wherein implanting comprises implanting an ion dose that does not exceed 5×10.sup.15 ions/cm.sup.2.

7. The method according to claim 1, wherein the electronic component is part of an integrated physical unclonable function device, the silicide electrical connection providing a current leakage path.

8. A method for manufacturing an electronic component which includes source and drain regions, a gate region between the source and drain regions, a first dielectric lateral spacing region against a first side of said gate region between the gate region and source region, and a second dielectric lateral spacing region against a second side of said gate region between the gate region and drain region, the method comprising: forming an electrical connection comprising a silicide on a surface of both the first and second dielectric lateral spacing regions, said electrical connecting configured to electrically connect the gate region to both the source region and the drain region.

9. The method according to claim 8, wherein forming said electrical connection comprises: implanting ions in the first and second dielectric lateral spacing regions; depositing a metal layer on the surface of the first and second dielectric lateral spacing regions; and performing a silicidation by said metal layer to form, by reaction of said metal layer with the implanted ions, said electrical connection.

10. The method according to claim 9, wherein depositing further comprises depositing said metal layer also on the source, drain and gate regions.

11. The method according to claim 9, wherein performing the silicidation comprises: applying a first heating at a first temperature; removing unreacted portions of said metal layer after the first heating; and applying a second heating at a second temperature; wherein said second temperature is higher than said first temperature.

12. The method according to claim 11, wherein the first temperature is of the order of 300° C.

13. The method according to claim 12, wherein the second temperature is of the order of 400° C.

14. The method according to claim 9, wherein implanting comprises implanting an ion dose that does not exceed 5×10.sup.13 ions/cm.sup.2.

15. The method according to claim 9, wherein implanting comprises implanting an ion dose that does not exceed 2×10.sup.14 ions/cm.sup.2.

16. The method according to claim 9, wherein implanting comprises implanting an ion dose that does not exceed 5×10.sup.15 ions/cm.sup.2.

17. The method according to claim 9, wherein the electronic component is part of an integrated physical unclonable function device, the silicide electrical connection providing a current leakage path.

18. An integrated physical unclonable function device, comprising: a plurality of electronic components, wherein each electronic component comprises: source and drain regions; a gate region between the source and drain regions; two dielectric lateral spacing regions against sides of the gate region; and an electrical connection on a surface of at least one of said two dielectric lateral spacing regions, said electrical connection configured to electrically connect the gate region to at least one of the source region and the drain region; wherein each electrical connection has a resistance; a resistance measuring circuit configured to measure the resistance of said electrical connection of each electronic component; a comparison circuit configured to compare the measured resistance of said electrical connection of each electronic component with a given reference resistance; and a generation circuit configured to generate a digital word in response to the comparisons made by the comparison circuit.

19. The device according to claim 18, wherein the electrical connection on the surface is a silicide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Other advantages and features of the invention will become apparent upon examining the detailed description of implementations and embodiments, which are in no way limiting, and of the appended drawings wherein:

[0047] FIG. 1 illustrates a sectional view of an integrated circuit;

[0048] FIG. 2 is a sequential diagram of a method for manufacturing an integrated circuit;

[0049] FIGS. 3 to 11 show the results of the various steps implemented in the manufacturing method of FIG. 2; and

[0050] FIG. 12 illustrates an integrated physical unclonable function device.

DETAILED DESCRIPTION

[0051] FIG. 1 illustrates a sectional view of an integrated circuit CI according to one embodiment.

[0052] The integrated circuit CI comprises at least one transistor TR and at least one electronic component CP according to one embodiment.

[0053] In particular, said at least one transistor TR can be a MOS transistor.

[0054] In FIG. 1, a single transistor TR and a single electronic component CP are shown for understanding purposes. Nevertheless, it is possible to provide an integrated circuit having several transistors and several electronic components.

[0055] In particular, each transistor TR comprises a drain region RDT and a source region RST formed in a semiconductor substrate SUB, in particular in the form of a planar layer. Each transistor TR also comprises a gate region RGT formed on the semiconductor substrate SUB between the drain RDT and source RST regions of this transistor TR. Although not specifically illustrated, the gate region RGT is insulated from the substrate SUB by an insulating layer (such as a gate oxide layer).

[0056] Each transistor TR also comprises two dielectric lateral spacing regions SPT1, SPT2 (also known to the person skilled in the art by the name “spacer” or “sidewall spacer”). The dielectric lateral spacing regions SPT1, SPT2 of each transistor TR are disposed against lateral sides of the gate region RGT of this transistor TR. These dielectric lateral spacing regions SPT1, SPT2 can be formed by silicon nitride.

[0057] Each transistor TR further comprises contacts CDT, CST and CGT formed respectively on the drain RDT, source RST and gate RGT regions of this transistor TR.

[0058] Likewise, each electronic component CP comprises a drain region RDC and a source region RSC formed in the semiconductor substrate SUB. Each electronic component CP also comprises a gate region RGC formed on the semiconductor substrate SUB between the drain RDC and source RSC regions of this electronic component CP. Although not specifically illustrated, the gate region RGC is insulated from the substrate SUB by an insulating layer (such as a gate oxide layer).

[0059] Furthermore, each electronic component CP also comprises two dielectric lateral spacing regions (spacers) SPC1, SPC2. The dielectric lateral spacing regions SPC1, SPC2 of each electronic component CP are disposed against lateral sides of the gate region RGC of this electronic component CP. These dielectric lateral spacing regions SPC1, SPC2 can be formed by silicon nitride.

[0060] Each electronic component CP further comprises contacts CDC, CSC, CGC formed respectively on the drain RDC, source RSC and gate RGC regions of this electronic component CP.

[0061] Each electronic component CP differs from a transistor TR in that it comprises at least one electrical connection CE configured to connect the gate region RGC to one or the other or both of the source region RSC and the drain region RDC.

[0062] This electrical connection CE is formed on the surface of at least one dielectric lateral spacing region SPC1, SPC2.

[0063] Preferably, this electrical connection CE is formed from a NiSi alloy. Nevertheless, alternatively, the electrical connection CE can be formed from an alloy of NiPtSi, CoSi, TiSi or for example NiGe, NiPtGe.

[0064] In particular, the electronic component CP may comprise a single electrical connection CE linking the gate region to the drain region, as shown in FIG. 1, or else a single electrical connection CE linking the gate region RGC to the source region RSC. This electrical connection CE is then formed on the surface of a single dielectric lateral spacing region SPC1, SPC2.

[0065] Alternatively, the electronic component may comprise two electrical connections CE, a first electrical connection linking the gate region RGC to the drain region RDC and a second electrical connection linking the gate region RGC to the source region RSC. These electrical connections CE are then formed on the surfaces of the two dielectric lateral spacing regions SPC1, SPC2.

[0066] Each electrical connection CE enables a leakage current to flow between the gate region RGC and the source region RSC and/or between the gate region RGC and the drain region RDC to which this electrical connection CE is linked.

[0067] Each electrical connection CE also has its own resistance.

[0068] Such an electronic component CP can be used for various applications for securing an integrated circuit CI depending on the leakage current that can be obtained by the electrical connection CE of this electronic component CP, as will be described below.

[0069] FIG. 2 shows a sequential diagram of a method for manufacturing an integrated circuit according to an embodiment. FIGS. 3 to 11 show the results of the various steps implemented in this manufacturing method.

[0070] The manufacturing method supports the manufacture of an integrated circuit as described above for FIG. 1. The manufacturing method thus supports the manufacture of an integrated circuit CI comprising at least one electronic component CP according to one implementation and at least one transistor TR, in particular at least one MOS transistor.

[0071] In particular, as will be described below, some steps of the manufacturing method are common for manufacturing each electronic component CP and each transistor TR. This permits a reduction in the number of steps required to manufacture the integrated circuit IC and supports reducing the cost of implementing the manufacturing method.

[0072] Thus, the method also comprises a step 10 wherein the gate region RGT, RGC of each transistor and of each electronic component is formed on a semiconductor substrate SUB. This includes the formation of a conductive gate and its associated insulating gate oxide layer.

[0073] The method comprises a step 11 wherein the source RST, RSC and drain RDT, RDC regions of each transistor TR and of each electronic component CP are formed in the semiconductor substrate SUB. In particular, the source RST, RSC and drain RDT, RDC regions of each transistor TR and of each electronic component CP are formed so that the gate region RGT, RGC of each transistor and of each electronic component is respectively disposed between the drain and source regions of this transistor and of this electronic component.

[0074] The method further comprises a step 12 wherein two dielectric lateral spacing regions SPT1, SPT2 and SPC1, SPC2 are formed on the semiconductor substrate SUB against the sides of the gate region RGT, RGC of each transistor TR and of each electronic component CP.

[0075] Steps 10 to 12 are well known to the person skilled in the art for forming transistors and will therefore not be further detailed here.

[0076] The result of these various steps is shown in FIG. 3.

[0077] The method then comprises a step 13 of forming a mask MSK allowing to protect each transistor TR during an ion implantation step 14 necessary to form said electrical connection CE of each electronic component CP. This ion implantation step 14 will be described in more detail below.

[0078] In order to form the mask, step 13 comprises forming (step 13-1) a planarized photosensitive resin RES layer on the integrated circuit CI. The result of this step is shown in FIG. 4.

[0079] Then, step 13 comprises removing (step 13-2) a portion of the planarized photosensitive resin RES layer on top of each electronic component CP. The removal of the portion of the planarized photosensitive resin RES on top of each electronic component CP can be accomplished by first exposing each portion of the planarized photosensitive resin RES covering each electronic component CP to light radiation. Then, a chemical developer is used to remove the portion of planarized photosensitive resin RES on top of each electronic component CP. The remaining planarized resin layer RES then forms the mask MSK, as shown in FIG. 5.

[0080] Then, in order to allow the manufacture of the electrical connection CE, the method comprises an ion implantation step 14 wherein ions are implanted in at least one of the dielectric lateral spacing regions SPC1, SPC2 of each electronic component CP. The remaining planarized resin layer RES of the mask MSK protects each transistor TR during this ion implantation step. This step is shown in FIG. 6.

[0081] The ion implantation is preferably carried out at an angle selected in particular according to the dielectric lateral spacing regions wherein the ions are to be implanted.

[0082] In particular, an ion implantation angle selected between −50° and 0° relative to a vertical axis allows ions to be implanted in the dielectric lateral spacing region SPC1 of each electronic component.

[0083] Furthermore, an ion implantation angle selected between 0° and +50° relative to a vertical axis allows ions to be implanted in the dielectric lateral spacing region SPC2 of each electronic component.

[0084] An ion implantation angle selected between −50° and +50° relative to a vertical axis allows ions to be implanted in each dielectric lateral spacing region SPC1, SPC2 of each electronic component CP.

[0085] The implanted ions are, for example, silicon ions Si+, as shown in FIG. 6. Nevertheless, alternatively, it is possible to implant any type of ion reacting with a metal layer MT used for a silicidation step, as will be described below. For example, when the metal layer used for silicidation is a nickel layer, it is possible to implant germanium ions because the germanium ions react with the nickel.

[0086] Then, the method comprises a step 15 wherein the remaining planarized resin layer RES is removed. The result of this step 15 is shown in FIG. 7. The removal of the remaining planarized resin layer can be carried out as described previously. The following steps of the manufacturing method are then common for each transistor TR and each electronic component CP.

[0087] The method then comprises a step 16, wherein a silicidation is carried out. This silicidation forms contacts CDT, CST, CGT respectively on the drain RDT, source RST and gate RGT regions of each transistor TR, as well as forms contacts CDC, CSC, CGC respectively on the drain RDC, source RSC and gate RGC regions of each electronic component CP. The silicidation also forms said electrical connection CE of each electronic component CP.

[0088] In particular, the silicidation comprises a deposition (step 16-1) of a metal layer MT on the integrated circuit CI, in particular on the source RST, RSC, drain RDT, RDC and gate RGT, RGC regions of each transistor TR and of each electronic component CP, as well as on the dielectric lateral spacing regions SPT1, SPT2, SPC1, SPC2 of each transistor TR and of each electronic component CP. Preferably, the metal layer MT used is a nickel layer. Nevertheless, alternatively, it is also possible to provide for using a layer of Ti, Co, Yb, Pt, Ni(Pt), Ru. The result of this deposition is shown in FIG. 8.

[0089] The silicidation then comprises a first heating (step 16-2) of the integrated circuit CI and of the metal layer MT. During this first heating step 16-2, the integrated circuit CI and the metal layer MT are heated to a temperature comprised between 240° C. and 350° C., in particular of the order of 300° C. Such a temperature enables the diffusion of the metal MT into the source RST, RSC, drain RDT, RDC and gate RGT, RGC regions of each transistor TR and of each electronic component CP. The metal MT can then react with source RST, RSC, drain RDT, RDC and gate RGT, RGC regions to manufacture the contacts CST, CSC, CDT, CDC, CGT and CGC. In particular, when the metal layer MT is made of nickel and the semiconductor substrate SUB is made of silicon, the first heating creates a Ni.sub.xSi phase, with x greater than or equal to 1, on the surface of the source RST, RSC, drain RDT, RDC and gate RGT, RGC regions.

[0090] Such a temperature also supports the diffusion of the metal MT on the surface of the dielectric lateral spacing regions SPC1, SPC2. The metal can then react with the ions implanted in these dielectric lateral spacing regions SPC1, SPC2.

[0091] In particular, the nickel layer MT is configured to react with the implanted silicon ions so as to obtain a Ni.sub.xSi phase.

[0092] Furthermore, the temperature of the first heating step 16-2 is configured to reduce a risk of obtaining a narrow line effect.

[0093] The result of this first heating is shown in FIG. 9.

[0094] The silicidation step 16 then comprises a removal (step 16-3) of the metal layer MT by a selective wet etching method. The removal step 16-3 of the metal layer allows the metal layer MT to be taken off without removing the metal reacted with the implanted ions. In particular, the removal is carried out using a mixture of sulfuric acid (H.sub.2SO.sub.4) and hydrogen peroxide (H.sub.2O.sub.2). The result of this removal step 16-3 is shown in FIG. 10.

[0095] The silicidation step 16 then comprises a second heating (step 16-4) to a temperature above the temperature used for the first heating. In particular, during the second heating, the integrated circuit is heated to a temperature comprised between 360° C. and 450° C., in particular of the order of 400° C.

[0096] The second heating step 16-4 causes a modification of the areas having a Ni.sub.xSi phase into a NiSi alloy. This NiSi alloy then forms the contacts CDT, CDC, CST, CSC, CGT, CSC on top of the drain RDT, RDC, source RST, RSC and gate RGT, RGC regions of each transistor TR and of each electronic component CP, as well as the electrical connection CE of each electronic component CP.

[0097] Thus, once this second heating step 16-4 has been completed, each transistor TR and each electronic component CP are obtained, as shown in FIG. 11.

[0098] In such a method, the steps of manufacturing a transistor TR are commonly carried out with some steps of manufacturing an electronic component CP. By performing these steps together, it is possible to optimize the method for manufacturing each transistor TR and each electronic component CP. In particular, because of these common manufacturing steps between the manufacture of a transistor TR and that of an electronic component CP, the manufacture of an electronic component CO requires only one additional step compared to the manufacture of a transistor TR. This additional step is the step 14 of implanting ions on the surface of at least one dielectric lateral spacing region. A mask is nevertheless also applied to each transistor TR to protect them during this ion implantation step 14.

[0099] Nevertheless, alternatively, it is possible to manufacture each electronic component CP separately in isolation from the transistors TR, for example by first forming each electronic component CP then forming the transistors TR (or vice versa).

[0100] Moreover, as indicated above, the electronic component CP can be intended for various applications for securing an integrated circuit CI. In particular, the leakage current resulting from the electrical connection CE of the electronic component CP is selected according to the selected application of the electronic component CP.

[0101] The leakage current of the electrical connection CE depends on its own resistance. However, the resistance of the electrical connection CE depends on the number of ions implanted in the dielectric lateral spacing regions SPC1, SPC2. Thus, the number of ions to be implanted in the dielectric lateral spacing regions SPC1, SPC2 depends on the selected application of the electronic component.

[0102] In particular, the number of ions to be implanted can be selected in order to be able to obtain an electronic component CP which can be used as a false transistor. The number of ions to be implanted is then selected to allow to obtain an electronic component CP having enough electrical connection to form a short circuit.

[0103] For example, the implantation is carried out so as to implant 5×10.sup.15 ions/cm.sup.2.

[0104] The electrical connection CE obtained is difficult to be detected. Thus, it is difficult for a third party to determine whether the electronic component CP is a transistor TR or not, due to the similar structure between the electronic component CP and a transistor TR. It is then difficult for this third party to reverse engineer the integrated circuit IC.

[0105] Moreover, the number of ions to be implanted can be selected in order to be able to obtain an electronic component CP which can be used for a slow discharge application. The leakage current permitted by the electrical connection CE then allows for a slow discharge to occur.

[0106] For example, the implantation can be carried out so as to implant 2×10.sup.14 ions/cm.sup.2. The leakage current of the electronic component CP is, in particular, comprised between 1 pA and 1 μA, for example of the order of 100 pA. The leakage current can therefore be used for a slow discharge.

[0107] Moreover, the number of ions to be implanted can be selected in order to be able to obtain an electronic component CP which can be used in an integrated physical unclonable function device DI.

[0108] For example, the implantation is carried out so as to implant 5×10.sup.13 ions/cm.sup.2. Such an ion implantation can produce an electronic component having a relatively low leakage current, in particular less than 10 nA.

[0109] The resistance of the electrical connection CE of several electronic components CP manufactured according to this same manufacturing method is variable according to these electronic components CP. It is then possible to use this variability of the resistance of the electrical connection CE of the electronic components CP in an integrated physical unclonable function device DI.

[0110] More particularly, FIG. 12 illustrates an integrated physical unclonable function device DI. This integrated device DI comprises a plurality of electronic components CP1, . . . , CPn, such as the electronic component CP described above. The electrical connections CE of the electronic components CP1, . . . , CPn have a resistance which may vary among the various electronic components.

[0111] The integrated device DI also comprises measurement circuit MM configured to measure the resistance of the electrical connection CE of each electronic component CP1, . . . , CPn.

[0112] The integrated device further comprises a comparison circuit CM configured to compare the measured resistance of the electrical connection CE of each electronic component CP1, . . . , CPn with a reference resistance. The reference resistor can be formed by an electronic component CPr such as the electronic component CP described above.

[0113] The integrated device DI also comprises a generation circuit GM configured to generate a digital word DW from the results of the comparisons made by the comparison circuit.

[0114] The digital word DW that can be generated by the generation circuit GM comprises a plurality of bits.

[0115] In particular, the generation circuit GM is configured to attribute a value to each bit of the digital word DW depending on the results of the comparisons that can be carried out by the comparison circuit CM.

[0116] Thus, each bit of the digital word is associated with a given electronic component CP1, . . . , CPn, the value of this bit depending on the result of the comparison between the value of the resistance of the electrical connection CE of this electronic component and the reference resistance.

[0117] For example, the generation circuit GM is configured to attribute a value ‘0’ to a bit when the result of the comparison of the resistance of the electrical connection of the electronic component CP1, . . . , CPn associated with this bit and the reference resistance shows that the resistance of the electrical connection CE of the electronic component CP1, . . . , CPn used for this comparison is less than the reference resistance.

[0118] The generation circuit GM is then also configured to attribute a value ‘1’ to this bit when the result of said comparison shows that the value of the resistance of the electrical connection CE of the electronic component CP1, . . . , CPn is greater than the reference resistance.

[0119] The comparison circuit CM and the generation circuit GM can be implemented by a processing unit UT, such as a microprocessor.

[0120] The binary words DW that can thus be generated may then be used to develop encryption keys for example.

[0121] For example, an integrated device comprising 128 electronic components CP1, . . . , CPn can be used in order to obtain a 128-bit digital word DW.