EXCHANGE OF DATA BETWEEN A NFC READER AND A DUAL NFC INTERFACE TRANSPONDER

Abstract

In an embodiment an apparatus includes a contactless transponder including a contactless interface and a wired interface, wherein the contactless transponder is configured to communicate with a contactless reader according to a contactless protocol through the contactless interface, a wired communication bus connected to the wired interface and at least one module connected to the bus, wherein the transponder is configured so that the reader is a master on the bus when the reader and the transponder communicate.

Claims

1-41. (canceled)

42. An apparatus comprising: a contactless transponder including a contactless interface and a wired interface, wherein the contactless transponder is configured to communicate with a contactless reader according to a contactless protocol through the contactless interface; a wired communication bus connected to the wired interface; and at least one module connected to the bus, wherein the transponder is configured so that the reader is a master on the bus when the reader and the transponder communicate.

43. The apparatus according to claim 42, wherein the at least one module is configured to directly communicate with the reader through the transponder.

44. The apparatus according to claim 42, wherein the transponder comprises pass-through circuitry configured to implement a pass-through function for message exchange between the at least one module the reader.

45. The apparatus according to claim 44, wherein the reader is configured to initiate commands within frames consistent with the contactless protocol, and wherein the pass-through circuitry is configured to transform the commands into commands on the bus consistent with a protocol used on the bus.

46. The apparatus according to claim 44, wherein the pass-through circuitry comprises a first volatile memory configured to buffer data payload of commands received from the reader through the contactless interface and data payload of responses intended to be sent to the reader through the contactless interface.

47. The apparatus according to claim 46, wherein the first volatile memory comprises at least one buffer.

48. The apparatus according to claim 46, wherein the pass-through circuitry further comprises a second volatile memory configured to store control data, and wherein the pass-through circuitry is configured to implement the pass-through function for message exchange between the reader and the at least one module on basis of the control data.

49. The apparatus according to claim 48, wherein the second memory comprises a plurality of registers.

50. The apparatus according to claim 48, wherein the control data comprises first control data sent in or deduced from data payloads of some of commands received from the reader.

51. The apparatus according to claim 48, wherein the pass-through circuitry further comprises: a first state machine configured to: cooperate with the reader through the contactless interface, and write to or read from the first memory and a part of the second memory based on commands received from the reader; and a second state machine configured to: cooperate with the bus through the wired interface based on a content of a part of the second memory, and write to or read first the first memory and a part of the second memory.

52. The apparatus according to claim 51, wherein the second state machine is configured to: read the data payload of commands from the first volatile memory and to execute them on the bus, and manage a clock and all bus protocol signaling information.

53. The apparatus according to claim 52, wherein the second state machine is configured to read the bus and to store them in the first volatile memory in order to be read by the first state machine.

54. The apparatus according to claim 42, wherein the transponder is configured implement a half-duplex data exchange mechanism on a side of the contactless interface.

55. The apparatus according to claim 42, wherein the bus is an I.sup.2C bus.

56. The apparatus according to claim 45, wherein the commands received from the reader comprises at least one request of a write operation to the at least one module or at least one request of a read operation to the at least one module.

57. The apparatus according to claim 56, wherein the at least one request of a write operation to the at least one module comprises an address of the at least one module and data to be written in the at least one module, and wherein the at least one request of a read operation to the at least one module comprises a number of bytes to be read and the address of the at least one module.

58. The apparatus according to claim 50, wherein the control data comprises data defining whether a command from the reader is a write operation or a read operation in the at least one module.

59. The apparatus according to claim 58, wherein the control data comprises data chosen from data defining a presence or the absence of an operation to be executed on the bus, data indicating whether an execution of a read operation requested by the reader is terminated, data indicating whether a result of a read operation requested by the reader is stored in the transponder, or data indicating whether a read or write operation requested by the reader is successful.

60. The apparatus according to claim 42, wherein the bus is a SPI bus.

61. The apparatus according to claim 45, wherein the commands received from the reader comprises at least one write command or at least one request of a read command.

62. The apparatus according to claim 60, wherein control data comprises data defining configuration of the SPI bus.

63. The apparatus according to claim 62, wherein the transponder comprises a shift register connected to the bus, and in a half-duplex transmission mode, a second state machine is configured to control a direction of the connection of the shift register on the bus.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0154] Other advantages and features of the invention will appear in the detailed description below and in the appended drawings which are not limitative, in which:

[0155] FIG. 1, already described, illustrates the prior art;

[0156] FIGS. 2-25 illustrate embodiments using an I.sup.2C bus; and

[0157] FIGS. 26-52 illustrate embodiments using a SPI bus.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0158] As shown on FIG. 2, which illustrates an example of a system SYS according to embodiments, a NFC/RFID reader RD can act as the I.sup.2C master of the application or apparatus APP, in place of a microcontroller.

[0159] In other words the reader RD is configured to directly communicate with slave modules D1-D4 of the apparatus APP through a contactless interface INT1 of a NFC/RFID dual interface transponder (or tag) TG, i.e. without passing through any microcontroller.

[0160] Although the reader RD is not directly connected to the I.sup.2C bus BS, the reader RD can be considered to be actually the master of the application or the master on the I.sup.2C bus, because it initiates commands within RF frames, and those commands will be transformed into I.sup.2C commands the I.sup.2C bus consistent with the I.sup.2C protocol.

[0161] The I.sup.2C interface INT2 of the tag, which is actually connected to the I.sup.2C bus BS, is a master interface.

[0162] Thus it can be also said that the reader is the master on the bus BS through the I.sup.2C master interface INT2.

[0163] As shown on FIG. 3, an example of a NFC/RFID dual interface transponder (or tag) according to embodiments integrates:

[0164] the RF contactless interface INT1

[0165] the I.sup.2C interface INT2

[0166] A non-volatile memory NVM, for example an EEPROM,

[0167] First volatile memory means, like a buffer BF (FIFO), to store I.sup.2C bytes,

[0168] Second volatile memory means, including a plurality of registers, for example the following ones:

[0169] A register RGW to store the number of I.sup.2C bytes to write.

[0170] A register RGD to store the number of I.sup.2C bytes to read.

[0171] A register RGC (containing one bit) to signal that I.sup.2C command is present in buffer BF.

[0172] A register RGR (containing one bit) to signal that I.sup.2C response is present in buffer BF.

[0173] A register RGK (containing one bit) to record Ack bit value. This register RGK is reset on read.

[0174] A state machine SM1 for RF pass through control.

[0175] A state machine SM2 for I.sup.2C pass through control.

[0176] Such a tag TG may be realized for example by an integrated circuit or chip, for example from an integrated circuit of the integrated circuits family having the reference ST25 at STMicroelectronics.

[0177] The I.sup.2C protocol is well known by the man skilled in the art and can be found in the I.sup.2C specification. Some features of the I.sup.2C protocol are now reminded.

[0178] The I.sup.2C bus uses two wires: serial data (SDA) and serial clock (SCL).

[0179] All I.sup.2C master and slave devices are connected with only those two wires.

[0180] A device acting as a master generates bus clock and initiates communication on the bus, other devices are slaves and respond to the commands on the bus.

[0181] In order to communicate with specific device, each slave device must have an address which is unique on the bus.

[0182] I.sup.2C master device does not need an address since no other (slave) device sends commands to the master.

[0183] Both signals SCL and SDA are bidirectional.

[0184] For each clock pulse one bit of data is transferred. The SDA signal can only change when the SCL signal is low. When the clock is high, the data should be stable.

[0185] Each I.sup.2C command initiated by master device starts with a START condition and ends with a STOP condition. For both conditions SCL has to be high. A high to low transition of SDA is considered as START and a low to high transition as STOP.

[0186] After the Start condition the bus is considered as busy.

[0187] After the Start condition the master can generate a repeated Start. This is equivalent to a normal Start and is usually followed by the slave I.sup.2C address.

[0188] FIGS. 4, 5 and 6 (extracted from I.sup.2C specification version 6.0, Apr. 4, 2014) illustrate features of the I.sup.2C protocol.

[0189] As illustrated in FIG. 4, data on the I.sup.2C bus is transferred in 8-bit packets (bytes). There is no limitation on the number of bytes, however, each byte must be followed by an acknowledge bit ACK from a slave device. This bit ACK signals whether the slave device is ready to proceed with the next byte. For all data bits and the acknowledge bit ACK, the master must generate clock pulses. If the slave device does not acknowledge transfer, this means that there is no more data or the device is not ready for the transfer yet. The master device must either generate Stop or Repeated Start condition.

[0190] Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL.

[0191] As illustrated in FIGS. 5 and 6, each slave device on the bus should have a unique 7-bit address.

[0192] The communication starts with the Start condition, followed by the 7-bit slave address and the data direction bit R/W.

[0193] If this bit R/W is 0 (FIG. 5) then the master will write to the slave device. Otherwise, if the data direction bit R/W is 1, the master will read from slave device (FIG. 6).

[0194] After the slave address and the data direction bit R/W are sent, the master can continue with reading or writing.

[0195] The communication is ended with the Stop condition which also signals that the I.sup.2C bus is free.

[0196] If the master needs to communicate with other slaves it can generate a repeated start with another slave address without generation Stop condition.

[0197] If the master only writes to the slave device. Then the data transfer direction is not changed (FIG. 5) The slave receiver acknowledges each byte.

[0198] If the master only needs to read from the slave device then it simply sends the I.sup.2C address with the R/W bit set to read. After this the master device starts reading the data. (FIG. 6).

[0199] At the moment of the first acknowledge, the master-transmitter becomes a master-receiver and the slave-receiver becomes a slave-transmitter. This first acknowledge A is still generated by the slave. The master generates subsequent acknowledges. The STOP condition is generated by the master, which sends a not-acknowledge just before the STOP condition.

[0200] FIGS. 7-11 explain an example of successive steps of the process of writing bytes into a slave module, those bytes being sent by the reader RD in order to be transmitted to a slave module of the apparatus APP.

[0201] As illustrated in FIG. 7, the NFC/RFID reader RD sends (step S7) a RF command 700 to the NFC/RFID tag to program the number of I.sup.2C bytes to be read.

[0202] The RF command 700 has a conventional structure compliant with the used RF protocol, and the number of I.sup.2C bytes to be read is included in the data payload of the RF command 700.

[0203] Here the value of the number of I.sup.2C bytes to be read is equal to 0 as there is no byte to be read on I.sup.2C bus.

[0204] This number of I.sup.2C bytes to be read is extracted from the RF command by the state machine SM1 (RF pass through control) and written in the register RGD by the state machine SM1 also (RF pass through control).

[0205] The register RGC and the register RGR contain a 0 value while the register RGK contains a 1 value.

[0206] As illustrated in FIG. 8, the NFC/RFID reader RD sends (step S8) a RF write command 800 to the NFC/RFID tag.

[0207] This RF command 800 contains I.sup.2C bytes to be written on I.sup.2C bus as well as the I.sup.2C slave address of the slave module intended for receiving those I.sup.2C bytes.

[0208] The I.sup.2C slave address and the I.sup.2C bytes form a complete I.sup.2C message intended for being delivering to the I.sup.2C bus but without I.sup.2C signaling information, i.e. without here the start and stop conditions.

[0209] The I.sup.2C slave address, which is the first byte, includes the R/W bit which is set to “write”.

[0210] This toggles the “I.sup.2C command in buffer” bit of the register RGC

[0211] In other words the register RGC is set to 1 by the state machine SM1 (RF pass through control).

[0212] The state machine SM1 (RF pass through control) stores the x I.sup.2C bytes into the buffer BF and updates the register RGW with this I.sup.2C number x of bytes to write in the designated slave module.

[0213] As illustrated in FIG. 9, the I.sup.2C pass-through state machine SM2 reads I.sup.2C bytes from buffer BF and sends them over the I.sup.2C bus to the corresponding slave module, adding signaling conditions (Start and Stop conditions).

[0214] This toggles the “I.sup.2C command in buffer” bit of the register RGC.

[0215] In other words the register RGC is reset to 0 by the state machine SM2.

[0216] The I.sup.2C pass-through state machine SM2 reads the Acknowledge bits from I.sup.2C bus sent by the I.sup.2C slave module and stores value 0 in the “Ack” register bit RGK.

[0217] As illustrated in FIG. 10, the NFC/RFID reader RD sends (step S10) a RF read command 1000 to the NFC/RFID tag to check if I.sup.2C operation is terminated (polling).

[0218] Upon receipt of this RF read command 1000, the RF state machine SM1 reads reading the “I.sup.2C command in buffer” bit contained in the register RGC.

[0219] The value of this bit is sent to the reader RD via a RF response 1001 having a conventional structure compliant with the used RF protocol.

[0220] If the value of this bit is 0, the I.sup.2C write operation is over.

[0221] As illustrated in FIG. 11, the NFC/RFID reader RD sends (step S11) a RF read command 1100 to the NFC/RFID tag to read the Acknowledge bit value contained in the register RGK to check if I.sup.2C write operation was successful. The write operation is successful if the Acknowledge bit value is 0.

[0222] More precisely, this RF command 1100 is processed by the RF state machine SM1 which reads the value contained in the register RGK, sends it via a RF response 1101 to the reader RD and resets the value of the register RGK to the value 1.

[0223] FIGS. 12-17 explain an example of successive steps of a reading process of bytes into a slave module of the apparatus APP in order to be transmitted to the NFC/RFIG reader RD.

[0224] As illustrated in FIG. 12, the NFC/RFID reader RD sends (step S12) a RF command 1200 to the NFC/RFID tag to program the number X of I.sup.2C bytes to be read on the I.sup.2C bus. The value of X is greater than 0 (some byte to be read on I.sup.2C bus).

[0225] The RF command 1200 has a conventional structure compliant with the used RF protocol, and the number X of I.sup.2C bytes to be read is included in the data payload of the RF command 700.

[0226] This number X of I.sup.2C bytes to be read is extracted from the RF command by the state machine SM1 (RF pass through control) and written in the register RGD by the state machine SM1 also (RF pass through control).

[0227] The register RGC and the register RGR contain a 0 value while the register RGK contains a 1 value.

[0228] As illustrated in FIG. 13, the NFC/RFID reader RD sends (step S13) a write command 1300 to the NFC/RFID tag TG.

[0229] This RF command 1300 contains the I.sup.2C slave address of the slave module intended to be read.

[0230] The I.sup.2C slave address form a complete I.sup.2C message intended for being delivering to the I.sup.2C bus but without I.sup.2C signaling information, i.e. without here the start and stop conditions.

[0231] The I.sup.2C slave address includes the R/W bit which is set to “read”.

[0232] This toggles the “I.sup.2C command in buffer” bit of the register RGC.

[0233] In other words the register RGC is set to 1 by the state machine SM1 (RF pass through control).

[0234] The state machine SM1 (RF pass through control) stores the I.sup.2C slave address into the buffer BF.

[0235] As illustrated in FIG. 14, the I.sup.2C pass-through state machine SM2 reads I.sup.2C slave address byte from buffer BF and sends it over the I.sup.2C bus through I.sup.2C interface INT2, adding signaling information (Start conditions and acknowledgment bits Acks).

[0236] This toggles the “I.sup.2C command in buffer” bit of the register RGC.

[0237] In other words the register RGC is reset to 0 by the state machine SM2. The I.sup.2C pass-through state machine SM2 reads the Acknowledge bit Ack from I.sup.2C bus and store value 0 in the “Ack” register bit RGK.

[0238] The I.sup.2C pass-through state machine reads all bytes from 1 to X from I.sup.2C bus, store them in the buffer BF, and sends Acks, Nack and Stop condition.

[0239] This toggles the “I.sup.2C response buffer” bit of the register RGR.

[0240] In other words the register RGR is set to 1 by the state machine SM2.

[0241] As illustrated in FIG. 15, the NFC/RFID reader RD sends (step S15) a read command 1500 to the NFC/RFID tag TG to check if I.sup.2C operation is terminated (polling).

[0242] Upon receipt of this RF read command 1500, the RF state machine SM1 reads reading the “I.sup.2C response in buffer” bit contained in the register RGR.

[0243] The value of this bit is sent to the reader RD via a RF response 1501 having a conventional structure compliant with the used RF protocol.

[0244] If the value of this bit is 1, then read operation is over.

[0245] As illustrated in FIG. 16, the NFC/RFID reader RD sends (step S16) a read command 1600 to the NFC/RFID tag to read the Acknowledge bit value contained in the register RGK to check if the slave module select operation was successful.

[0246] The slave module select operation is successful if the Acknowledge bit value is 0.

[0247] More precisely, this RF command 1600 is processed by the RF state machine SM1 which reads the value contained in the register RGK, sends it via a RF response 1601 to the reader RD and resets the value of the register RGK to the value 1.

[0248] As illustrated in FIG. 17, the NFC/RFID reader RD sends (step S17), a read command 1700 to the NFC/RFID tag TG to read the I.sup.2C bytes response contained in the buffer BF.

[0249] More precisely, this RF command 1700 is processed by the RF state machine SM1, which then sends the I.sup.2C byte1-I.sup.2C byteX in the payload data of a RF response 1601 to the reader RD and toggles the value of the register RGR to the value 0.

[0250] As it can be seen from explanations related to FIGS. 7-17, the registers RGD, RGW, RGC, RGR, RGK contain control (called also configuration) data (one or several bits) which permit for example to determine the presence or the absence of an operation to be executed, the type of operation (write or read operation) or the status of the operation (terminated for example) or the result of the operation (successful for example).

[0251] Those control registers are read and/or written [0252] by the RF state machine SM1 upon reception of a RF command (request) sent by the reader, or [0253] by the I.sup.2C state machine SM2.

[0254] More precisely, registers RGD, RGW and RGC are written by the RF state machine SM1.

[0255] For example if the register RGC contains value 0, it means that there is no I.sup.2C command to be executed by the I.sup.2C state machine SM2.

[0256] If the register RGC contains value 1, it means that there is an I.sup.2C command to be executed by the I.sup.2C state machine SM2, this command being either a write operation or a read operation.

[0257] The type of operation (read or write) is determined by the contents of registers RGD and RGW.

[0258] More precisely if the value contained in the register RGD is nul and the value contained in the register RGW in not nul, the operation requested by the reader is a write operation.

[0259] If the value contained in the register RGW is nul and the value contained in the register RGD in not nul, the operation requested by the reader is a read operation.

[0260] The register RGW and the register RGD are also read by the state machine SM2 to know the number of bytes to write or read in the designated slave module.

[0261] The register RGC is also read by the state machine SM2 to know if a command is to be executed on the bus and also written by the state machine SM2 when the execution of the command has started.

[0262] The register RGC is also read by the state machine SM1 upon request of the reader to know if the execution of a requested command is terminated.

[0263] The register RGR is written by the state machine SM2 to indicate that read bytes are stored in the buffer BF, and the register RGR is also read by the state machine SM1 upon request of the reader to check if the I.sup.2C read operation is terminated.

[0264] The register RGK (for example initially set to 1) is written by the state machine SM2 upon reception of Ack bits, read by the state machine SM1 upon request of the reader RD to check whether the read or write operation is successful, and reset to 1 by the state machine SM1.

[0265] Among those control data, the data contained in registers RGD and RGW are first control data sent within or deduced from the data payload of the commands sent by the reader and defining if a command from the reader is a write operation or a read operation in the designated slave module.

[0266] The data contained in register RGC is a control data defining the presence or the absence of an operation to be executed on said bus.

[0267] The data contained in register RGC is also a control data indicating whether the execution of a write operation requested by the reader is terminated and the data contained in register RGR is a control data indicating whether the execution of a read operation requested by the reader is terminated.

[0268] The data contained in register RGR is also a control data indicating whether the result of a read operation requested by the reader is stored in the transponder.

[0269] The data contained in the register RGK is a control data indicating whether a read or write operation requested by the reader is successful.

[0270] FIG. 18 details an example of the RF pass through state machine SM1 and FIG. 19 details an example of PC pass through state machine SM2, both permitting to implement the steps disclosed in FIGS. 7-17.

[0271] FIGS. 20-25 illustrate examples of apparatuses according to embodiments using an PC bus and a contactless transponder or tag according to embodiments, for example a tag or contactless transponder referenced ST25DV within the STMicroelectronics company having an integrated circuit modified for incorporating means of the embodiments.

[0272] More precisely, FIG. 20 illustrates a sensor 2000 without MCU (microcontroller). FIG. 21 illustrates a door lock 2100. FIG. 22 illustrates GPI/O extension 2200. FIG. 23 illustrates an analog sensor 2300 without MCU. FIG. 24 illustrates e-Label 2400 without MCU. FIG. 25 illustrates a very big memory tag 2500.

[0273] The embodiments are not limited to the above examples, but can be extended to other RFID technologies: UHF (ISO18000-6, ISO18000-63, EPC Gen2).

[0274] Further embodiments can be extended to other bus protocols.

[0275] An example of another possible protocol is SPI (Serial Peripheral Interface) (half duplex transmission.

[0276] or full duplex transmission) will be now explained more in details.

[0277] As shown on FIG. 26, which illustrates an example of a system SYS1 according to embodiments, a NFC/RFID reader RD1 can act as the SPI master of the application or apparatus APP1, in place of a microcontroller.

[0278] In other words the reader RD1 is configured to directly communicate with slave modules D1o-D40 of the apparatus APP1 through a contactless interface INT10 of a NFC/RFID dual interface transponder (or tag) TG1, i.e. without passing through any microcontroller.

[0279] Although the reader RD1 is not directly connected to the SPI bus BS1, the reader RD1 can be considered to be actually the master of the application or the master on the SPI bus, because it initiates commands within RF frames, and those commands will be transformed into SPI commands the SPI bus consistent with the SPI protocol.

[0280] The SPI interface INT20 of the tag, which is actually connected to the SPI bus BS1, is a master interface.

[0281] Thus it can be also said that the reader is the master on the bus BS1 through the SPI master interface INT20.

[0282] As shown on FIG. 27, an example of a NFC/RFID dual interface transponder (or tag) TG1 according to embodiments integrates:

[0283] First volatile memory means including a transmission (Tx) buffer (FIFO) BFT to store SPI bytes to be transmitted, and a reception (Rx) buffer (FIFO) BFR to store received SPI bytes;

[0284] Second volatile memory means including a plurality of registers, for example the following ones:

[0285] A register RGCF to store SPI configuration (clock phase/polarity, clock speed, bits order, full/half duplex transmission mode);

[0286] A register (counter) DCNT to store the total number of SPI bytes to transmit and receive;

[0287] A register (counter) TXCNT to store the number of bytes to transmit in half duplex transmission mode;

[0288] A shift register SR to store transmit and received data in full-duplex;

[0289] A register RGRT to store a bit to signal the SPI is ready to transmit (Tx buffer has been filled);

[0290] A register RGTC to store a bit to signal the SPI transmit/receive is completed (Tx buffer BIT has been emptied, Rx buffer BFR has been filled);

[0291] A first state machine SM10 for contactless (RF) pass through control;

[0292] A second state machine SM20 for SPI pass through control.

[0293] The SPI protocol is well known by the man skilled in the art.

[0294] Some features of the SPI protocol are reminded thereafter in relation with FIGS. 28-30.

[0295] As illustrated in FIG. 28, the master is connected to one or more slaves through 4 (in a full-duplex transmission mode) or more lines:

[0296] SCLK: clock.

[0297] MOSI: Master Output Slave Input to transmit data to a slave.

[0298] MISO: Master Input Slave Output to receive data from a slave.

[0299] SS: Slave Select line, (active low to select the slave).

[0300] In half-duplex transmission mode (so called 3 wire mode), data is transmitted and received on the same line (MOSI=MISO).

[0301] As mentioned above, SPI can be set up to operate with a single master and a single slave, and it can be set up with multiple slaves controlled by a single master. There are two ways to connect multiple slaves to the master. If the master has multiple slave select pins, the slaves can be wired in parallel. If only one slave select pin is available, the slaves can be daisy-chained.

[0302] The clock signal SCLK synchronizes the output of data bits from the master to the sampling of bits by the slave. One bit of data is transferred in each clock cycle, so the speed of data transfer is determined by the frequency of the clock signal. SPI communication is always initiated by the master since the master configures and generates the clock signal.

[0303] The master can choose which slave it wants to talk to by setting the slave's SS line to a low voltage level. In the idle, non-transmitting state, the slave select line is kept at a high voltage level.

[0304] The master sends data to the slave bit by bit, in serial through the MOSI line. The slave receives the data sent from the master at the MOSI pin. Data sent from the master to the slave is usually, but not compulsorily, sent with the most significant (MSB) bit first.

[0305] The slave can also send data back to the master through the MISO line in serial. The data sent from the slave back to the master is usually sent with the least significant (LSB) bit first.

[0306] Data is only valid during SS low.

[0307] As illustrated on FIG. 29, the SPI bus is full duplex based on exchange of data in a shift register.

[0308] Bits from the master shift register are pushed into the slave shift register.

[0309] Bits from the slave shift register are pushed in the master shift register at the same time.

[0310] As illustrated in FIG. 30, data is sampled on SCLK, with configurable phase CPHA and polarity CPOL.

[0311] More precisely, the clock signal SCLK in SPI can be modified using the properties of clock polarity and clock phase. These two properties work together to define when the bits are output and when they are sampled. Clock polarity can be set by the master to allow for bits to be output and sampled on either the rising or falling edge of the clock cycle. Clock phase can be set for output and sampling to occur on either the first edge or second edge of the clock cycle, regardless of whether it is rising or falling.

[0312] The steps for SPI data transmission are the following ones:

[0313] The master outputs the clock signal; The master switches the SS pin to a low voltage state, which activates the slave; The master sends the data one bit at a time to the slave along the MOSI line. The slave reads the bits as they are received; If a response is needed, the slave returns data one bit at a time to the master along the MISO line. The master reads the bits as they are received.

[0314] FIGS. 31 to 36 illustrate an example of a SPI full duplex transmission mode implemented by the system SYS1 according to embodiments.

[0315] As illustrated in FIG. 31, the NFC/RFID reader RD1 sends (step S31) a RF write command 3100 to the NFC/RFID tag to configure the SPI bus by writing the SPI configuration into the SPI configuration register RGCF.

[0316] SPI configuration contains the following information:

[0317] CLKPOL: clock polarity to be used,

[0318] CLKPH: clock phase to be used,

[0319] CLK freq: clock frequency to be used,

[0320] Bit Polarity: to select if shift register is sending data MSB first or LSB first,

[0321] Full/Half duplex mode selection (here full duplex mode).

[0322] The RF command 3100 has a conventional structure compliant with the used RF protocol, and the configuration information is included in the data payload of the RF command 3100.

[0323] This configuration information is extracted from the RF command by the state machine SM10 (RF pass through control) and written in the register RGCF by the state machine SM10 also (RF pass through control).

[0324] The register RGRT and the register RGTC contain a 0 value.

[0325] As illustrated in FIG. 32, the NFC/RFID reader RD1 sends (step S32) a RF write command 3200 to the NFC/RFID tag TG1.

[0326] This RF command 3200 contains SPI bytes to be transmitted on SPI bus.

[0327] This toggles the “SPI ready to Tx” bit of the register RGRT

[0328] In other words the register RGRT is set to 1 by the state machine SM10 (RF pass through control).

[0329] The state machine SM10 (RF pass through control) updates the counter DCNT with the number X of bytes to transmit on the SPI bus and writes into Tx buffer the X SPI bytes to be transmitted.

[0330] As illustrated in FIG. 33, once SPI Tx ready bit contained in register RGRT is set to 1, the SPI pass-through state machine SM2o does (step S33):

[0331] select the slave device by setting SS line low,

[0332] copy SPI bytes from Tx buffer BFT to the shift register SR and send them on the MOSI line to the slave,

[0333] read the MISO line from the slave and copy the SPI received bytes from the shift register SR into the Rx buffer BFR,

[0334] decrease SPI data counter DCNT and loop until it is null.

[0335] As illustrated in FIG. 34, once all Tx bytes are transmitted, the SPI pass-through state machine SM20 sets (step S34) the SPI Rx complete bit of the register RGTC to 1 and clears the SPI ready to Tx bit of the register RGRT to 0.

[0336] Rx buffer BFR now contains all the received bytes.

[0337] Tx buffer is empty (SPI data counter DCNT is null).

[0338] SS line is set to high to deselect the SPI slave.

[0339] More precisely, this RF command 3500 is processed by the RF state machine SM10 which reads the value contained in the register RGTC and sends it via a RF response 3501 to the reader RD1.

[0340] As illustrated in FIG. 36, the NFC/RFID reader RD1 sends (step S36) a read command 3600 to the NFC/RFID tag TG1 to read the SPI received bytes in the Rx buffer BFR.

[0341] More precisely, this RF command 3600 is processed by the RF state machine SM10 which reads the bytes contained in the Rx buffer BFR and sends them via a RF response 3601 to the reader RD1.

[0342] This toggles the “SPI Rx complete” bit contained in the register RGTC. In other words the RF state machine SM10 resets this bit to 0.

[0343] The NFC/RFID tag TG1 is now ready for a new SPI transmission.

[0344] FIGS. 37 to 44 illustrate an example of a SPI half-duplex transmission implemented by the system SYS1 according to embodiments.

[0345] As indicated above, in half-duplex transmission (so called 3 wire mode), data is transmitted and received on the same line.

[0346] The SPI state machine SM20 controls the direction of the output/input pin from/into the shift register SR.

[0347] As illustrated in FIG. 37, the NFC/RFID reader RD1 sends (step S37) a RF write command 3700 to the NFC/RFID tag TG1 to configure the SPI bus by writing the SPI configuration into the SPI configuration register RGCF.

[0348] SPI configuration contains the following information:

[0349] CLKPOL: clock polarity to be used,

[0350] CLKPH: clock phase to be used,

[0351] CLK freq: clock frequency to be used,

[0352] Bit Polarity: to select if shift register is sending data MSB first or LSB first,

[0353] Half duplex mode selection.

[0354] The RF command 3700 has a conventional structure compliant with the used RF protocol, and the configuration information is included in the data payload of the RF command 3700.

[0355] This configuration information is extracted from the RF command by the state machine SM10 (RF pass through control) and written in the register RGCF by the state machine SM1 also (RF pass through control).

[0356] The register RGRT and the register RGTC contain a 0 value.

[0357] As illustrated in FIG. 38, the NFC/RFID reader RD1 sends (step S38) a RF write command 3800 to the NFC/RFID tag TG1.

[0358] This RF command 3800 contains the number of SPI bytes to transmit on SPI bus.

[0359] The state machine SM10 (RF pass through control) updates the counter TXCNT with the number of bytes to transmit on the SPI.

[0360] The number of bytes to transmit corresponds to the number of byte that will be sent from the master to the slave. The SPI data line is configured as output during this time. Once this number of bytes has been transmitted, the SPI line is configured as input to receive the remaining number of bytes counted by SPI data counter register DCNT.

[0361] As illustrated in FIG. 39, the NFC/RFID reader RD1 sends (step S39) a RF write command 3900 to the NFC/RFID tag TG1.

[0362] This RF command 3900 contains SPI bytes to be transmitted on SPI bus.

[0363] This toggles the “SPI ready to Tx” bit of the register RGRT.

[0364] In other words the register RGRT is set to 1 by the state machine SM10 (RF pass through control).

[0365] The state machine SM10 (RF pass through control) writes into Tx buffer BFR the SPI bytes to be transmitted on the SPI bus and updates the counter DCNT with the number of bytes stored in the Tx buffer BFT. This represent the total number of bytes that goes through the SPI bus in output and input.

[0366] NFC/RFID reader RD1 has to put “dummy” Tx bytes to reflect the total number of bytes transmitted in output and input.

[0367] As illustrated in FIG. 40, once SPI Tx ready bit contained in register RGRT is set to 1, the SPI pass-through state machine SM2o does (step S40):

[0368] select the slave device by setting SS line low,

[0369] copy SPI bytes from Tx buffer BFT to the shift register SR and send them on the MOSI line to the slave,

[0370] decrease SPI data counter DCNT and loop until counter TXCNT is null.

[0371] As illustrated in FIG. 41, once all Tx bytes are transmitted, the SPI pass-through state machine SM20 sets (step S41) the SPI data line to input and starts receiving the Rx bytes 4100.

[0372] More precisely, the state machine SM2o reads the line from the slave and copies the SPI received bytes from the shift register SR into the Rx buffer BFR, and decreases SPI data counter DCNT and loop until it is null.

[0373] As illustrated in FIG. 42, once all Tx bytes are transmitted, the SPI pass-through state machine SM20 sets (step S42) the SPI Rx complete bit of the register RGTC to 1 and clears the SPI ready to Tx bit of the register RGRT to 0.

[0374] Rx buffer BFR now contains all the received bytes.

[0375] Tx buffer is empty (SPI data counter DCNT is null).

[0376] SS line is set to high to deselect the SPI slave.

[0377] As illustrated in FIG. 43, the NFC/RFID reader RD1 sends (step S43) a RF read command 4300 to the NFC/RFID tag TG1 to read the “SPI Rx complete” bit contained in the register RGTC to check if SPI operation is terminated. If value is 1, the SPI write operation is over.

[0378] More precisely, this RF command 4300 is processed by the RF state machine SM10 which reads the value contained in the register RGTC and sends it via a RF response 4301 to the reader RD1.

[0379] As illustrated in FIG. 44, the NFC/RFID reader RD1 sends (step S44) a read command 4400 to the NFC/RFID tag TG1 to read the SPI received bytes in the Rx buffer BFR.

[0380] More precisely, this RF command 4400 is processed by the RF state machine SM10 which reads the bytes contained in the Rx buffer BFR and sends them via a RF response 4401 to the reader RD1.

[0381] This toggles the “SPI Rx complete” bit contained in the register RGTC. In other words the RF state machine SM10 resets this bit to 0.

[0382] The NFC/RFID tag TG1 is now ready for a new SPI transmission.

[0383] As it can be seen from explanations related to FIGS. 31-44, the registers RGCF, RGRT, RGTC, DCNT, TXCNT contain control (called also configuration) data (one or several bits) which permit for example to determine the SPI configuration, or to indicate a status “ready to transmit” or the status of the operation (terminated for example) or numbers of bytes to transmit.

[0384] Those control registers are read and/or written [0385] by the RF state machine SM10 upon reception of a RF command (request) sent by the reader, or [0386] by the SPI state machine SM20.

[0387] More precisely, registers RGCF, RGRT, DCNT, TXCNT and RGTC are written by the RF state machine SM10.

[0388] For example if the register RGRT contains value 0, it means that there is no SPI command to be executed by the SPI state machine SM20.

[0389] If the register RGRT contains value 1, it means that there is a SPI command to be executed by the SPI state machine SM20.

[0390] The number of bytes to transmit on the SPI bus is determined by the contents of registers DCNT and eventually TXCNT.

[0391] In this respect the registers DCNT and TXCNT are also read by the state machine SM20.

[0392] The register RGRT is also read by the state machine SM20 to know if a command is to be executed on the bus and also written by the state machine SM20 when the execution of the command is terminated.

[0393] The register RGTC is written by the SPI state machine SM20 when the execution of the command is terminated and is read by the state machine SM10 upon request of the reader to know if the execution of a requested command is terminated.

[0394] This register RGTC is also reset by the state machine SM10.

[0395] Among those control data, the data contained in registers RGCF, DCNT and TXCNT are first control data sent within or deduced from data payloads of commands sent by the reader.

[0396] FIG. 45 details an example of the RF pass through state machine SM10 and FIG. 46 details an example of SPI pass through state machine SM20, both permitting to implement the steps disclosed in FIGS. 31-44.

[0397] FIGS. 47-52 illustrate examples of apparatuses according to embodiments using a SPI bus and a contactless transponder or tag according to embodiments, for example a tag or contactless transponder referenced ST25DV within the STMicroelectronics company having an integrated circuit modified for incorporating means of the embodiments.

[0398] More precisely, FIG. 47 illustrates a sensor 4700 without MCU. FIG. 48 illustrates a door lock 4800. FIG. 49 illustrates GPI/O extension 4900. FIG. 50 illustrates an analog sensor 5000 without MCU. FIG. 51 illustrates e-Label 5100 without MCU. FIG. 52 illustrates a very big memory tag 5200.