Package structure of common-source common-gate gallium nitride field-effect transistor

Abstract

A package structure of a common-source common-gate gallium nitride field-effect transistor is disclosed, including a lead frame. A gallium nitride field-effect transistor and a metal oxide semiconductor are directly disposed on the lead frame. The gallium nitride field-effect transistor includes a first matrix directly disposed on the lead frame. A first drain, a first gate, and a first source are disposed on a surface side of the first matrix, and the first drain and the first gate are separately electrically connected to the lead frame. The metal oxide semiconductor includes a second matrix directly disposed on the lead frame. A second drain, a second gate, and a second source are disposed on a surface side of the second matrix, the second drain is directly electrically connected to the first source, and the second gate and the second source are separately electrically connected to the lead frame.

Claims

1. A package structure of a common-source common-gate gallium nitride field-effect transistor, comprising: a lead frame; a gallium nitride field-effect transistor, comprising a first body directly disposed on the lead frame, wherein a first drain, a first gate, and a first source are disposed on a surface side of the first matrix, and the first drain and the first gate are separately electrically connected to the lead frame; and a metal oxide semiconductor, comprising a second body directly disposed on the lead frame, wherein a second drain, a second gate, and a second source are disposed on a surface side of the second matrix, and the second drain is directly electrically connected to the first source, and the second gate and the second source are separately electrically connected to the lead frame.

2. The package structure of the common-source common-gate gallium nitride field-effect transistor according to claim 1, wherein a package body covers the lead frame, the gallium nitride field-effect transistor, and the metal oxide semiconductor.

3. The package structure of the common-source common-gate gallium nitride field-effect transistor according to claim 2, wherein the lead frame is provided with a pin extending out of the package body.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic structural diagram according to the present invention; and

(2) FIG. 2 is a schematic structural diagram of a conventional structure.

DESCRIPTION OF THE EMBODIMENTS

(3) FIG. 1 shows a package structure of a common-source common-gate the gallium nitride field-effect transistor according to the present invention. The package structure includes a lead frame 1. A gallium nitride field-effect transistor 2 (GaN FET) and a horizontal metal oxide semiconductor 3 (MOS) are directly disposed on the lead frame 1. The gallium nitride field-effect transistor 2 includes a first matrix 21 directly disposed on the lead frame 1, a first drain 22, a first gate 23, and a first source 24 are disposed on a surface side of the first matrix 21, and the first drain 22 and the first gate 23 are separately electrically connected to the lead frame 1. The metal oxide semiconductor 3 includes a second matrix 31 directly disposed on the lead frame 1, a second drain 32, a second gate 33, and a second source 34 are disposed on a surface side of the second matrix 31, and the second gate 33 and the second source 34 are separately electrically connected to the lead frame 1.

(4) Accordingly, the first source 24 of the gallium nitride field-effect transistor 2 is directly electrically connected to the second drain 32 of the metal oxide semiconductor 3, to form a common-source common-gate form. Next, a package body 4 covers the lead frame 1, the gallium nitride field-effect transistor 2, and the metal oxide semiconductor 3, and a pin 11 extending out of the package body 4 extends out of the lead frame 1.

(5) Based on the foregoing structure, in the present invention, the first source 24 of the gallium nitride field-effect transistor 2 is directly electrically connected to the second drain 32 of the metal oxide semiconductor 3. Therefore, a structure of a metal coating and a ceramic substrate in a conventional transistor is omitted, thereby simplifying the structure and a manufacturing process, and further reducing costs.