Multi-Tier Processor/Memory Package

Abstract

A packaged IC includes a fanout layer, an Application Processor (AP) die having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die Process, and high bandwidth memory coupled to a second surface of the RDL and configured to communicate wirelessly with the AP die. The packaged IC further includes an encapsulant surrounding a substantial portion of the high bandwidth memory, the RDL, and the AP die, the encapsulant contacting the fanout layer on a first side and having an exposed second side, a plurality of conductive posts extending from the fanout layer to the RDL through a portion of the encapsulant, and a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the exposed second side of the encapsulant.

Claims

1. A packaged Integrated Circuit (IC) comprising: a fanout layer; an Application Processor (AP) die having a first surface adjacent to a first surface of the fanout layer; a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die; high bandwidth memory coupled to a second surface of the RDL and configured to communicate wirelessly with the AP die; an encapsulant surrounding at least a portion of the high bandwidth memory, the RDL, and the AP die, a first side of the encapsulant contacting the fanout layer and a second side of the encapsulant being at least partially exposed; a plurality of conductive posts extending from the fanout layer to the RDL through a portion of the encapsulant; and a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the second side of the encapsulant.

2. The packaged IC of claim 1, wherein the RDL includes electrical conductors adapted to enable wireless communication between the high bandwidth memory and the AP die.

3. The packaged IC of claim 1, wherein a portion of the high bandwidth memory resides outside a footprint of the AP die.

4. The packaged IC of claim 1, wherein the high bandwidth memory resides within a footprint of the AP die.

5. The packaged IC of claim 1, further comprising a dummy silicon substrate adjacent to the high bandwidth memory.

6. The packaged IC of claim 1, further comprising: a ball grid array coupled to the plurality of TMVs; and Package on Package (POP) memory coupled to the ball grid array.

7. The packaged IC of claim 1, further comprising a PCB ball grid array coupled to a second surface of the fanout layer.

8. A method for constructing a packaged Integrated Circuit (IC) comprising: fabricating a second plurality of through mold vias (TMVs) on a carrier; placing a high bandwidth memory on the carrier; molding and polishing a second encapsulant to expose the second plurality of TMVs; fabricating a redistribution layer (RDL) on the second encapsulant that couples to the second plurality of TMVs; fabricating a first plurality of TMVs on the redistribution layer; placing an application processor (AP) die on the redistribution layer; molding and polishing a first encapsulant to expose the first plurality of TMVs; fabricating a fanout layer on the first encapsulant, thereby at least partially forming the packaged IC; and demounting the packaged IC from the carrier.

9. The method of claim 8, wherein the RDL includes electrical conductors adapted to enable wireless communication between the high bandwidth memory and the AP die.

10. The method of claim 8, wherein a portion of the high bandwidth memory resides outside a footprint of the AP die.

11. The method of claim 8, wherein the high bandwidth memory resides within a footprint of the AP die.

12. The method of claim 8, further comprising placing a dummy silicon substrate adjacent to the high bandwidth memory, wherein the second encapsulant surrounds at least a portion of the dummy silicon substrate.

13. The method of claim 8, further comprising: forming a ball grid array on the second encapsulant that couples to the plurality of TMVs; and placing Package on Package (POP) memory on the ball grid array.

14. The method of claim 8, further comprising forming a ball grid array on the redistribution layer.

15. A packaged Integrated Circuit (IC) comprising: a fanout layer; an Application Processor (AP) die having a first surface adjacent to a first surface of the fanout layer; a plurality of conductive posts extending from the fanout layer; a first encapsulant surrounding at least a portion of the AP die and the plurality of conductive posts, the first encapsulant contacting the fanout layer on a first side and having an exposed second side; a first plurality of Through Mold Vias (TMVs) extending from the fanout layer through the first encapsulant; a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die; high bandwidth memory coupled to a second surface of the RDL, the high bandwidth memory configured to communicate wirelessly with the AP die; a second encapsulant surrounding at least a portion of the high bandwidth memory and the RDL; and a second plurality of TMVs extending from the first plurality of TMVs through the second encapsulant.

16. The packaged IC of claim wherein the RDL includes electrical conductors adapted to enable the high bandwidth memory to communicate wirelessly with the AP die.

17. The packaged IC of claim 15, wherein the high bandwidth memory resides within a footprint of the AP die.

18. The packaged IC of claim 15, wherein a portion of the high bandwidth memory resides outside of a footprint of the AP die.

19. The packaged IC of claim 15, further comprising: a ball grid array coupled to the plurality of TMVs; and Package on Package (POP) memory coupled to the ball grid array.

20. The packaged IC of claim 15, further comprising a PCB ball grid array coupled to a second surface of the fanout layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

[0015] FIG. 1 is a sectional side view illustrating a packaged integrated Circuit (IC) constructed according to a first described embodiment.

[0016] FIG. 2 is a sectional side view illustrating a packaged IC constructed according to a second described embodiment

[0017] FIG. 3 is a diagrammatic top view of a portion of the packaged IC of FIG. 2.

[0018] FIG. 4 is a sectional side view illustrating a packaged IC constructed according to a third described embodiment.

[0019] FIG. 5 is a sectional side view illustrating a packaged IC constructed according to a fourth described embodiment.

[0020] FIG. 6 is a diagrammatic top view of a portion of the packaged IC of FIG. 5.

[0021] FIG. 7 is a sectional side view illustrating a packaged IC constructed according to a fifth described embodiment.

[0022] FIG. 8 is a flow chart illustrating operations for constructing a packaged IC according to an embodiment of the present disclosure.

[0023] FIGS. 9A-J are diagrammatic sectional side views of the packaged IC during manufacture consistent with the operations of FIG. 8.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0024] FIG. 1 is a sectional side view illustrating a packaged integrated Circuit (IC) constructed according to a first described embodiment. The packaged IC100 includes a fanout layer 102 having signal conductors and vias 106 and power conductors and vias 104. The fanout layer may be formed in a semiconductor manufacturing process. An Application Processor (AP) die 108 has a first surface residing substantially adjacent a first surface of the fanout layer 102. The AP die mob may be a video processor, a communications processor, a general-purpose processor, an application specific processor, or another type of processor. The AP die 108 may mount directly to the fanout layer 102 or mount upon an intermediary layer.

[0025] A fanout Redistribution Layer (RDL) 110 having a first surface couples to a second surface of the AP die 108. The RDL 110 may also be formed in a semiconductor manufacturing process and provides power conductors formed therein that couple to the power conductors and vias 104 of the fanout layer 102. Such power coupling may be serviced by a conductive post All of these power and/or signal conductors may be formed of Copper with dimensions greater than one micrometer, for example.

[0026] High bandwidth memory 112 couples to a second surface of the RIM, 110 and is configured to communicate wirelessly 124 with the AP die 108, e.g., via inductive coupling, capacitive coupling or Radio Frequency (RF) coupling. The high bandwidth memory 112 may include antennas, contacts, and/or coils to assist with the wireless communications 124. The AP die 108 may also include antennas, contacts, and/or coils to support wireless communications with the high bandwidth memory 112. In an alternate construct, the antennas, contacts, and/or coils may be formed external to the high bandwidth memory and/or the AP die 108 and electrically couple thereto.

[0027] The high bandwidth memory 112 may be any type of memory that supports the high bandwidth storage requirements of the AP die 108. The wireless communications 124 supports the transfer of data on a high bandwidth basis between the AP die 108 and the high bandwidth memory 112 with reduce power consumption as compared to wired connections. The communication coil could be embedded into the metal layers of the high bandwidth memory 112, and the metal layers of the AP die 108. For example, the high bandwidth memory 112 may be RAM, ROM, static RAM, optical memory, or another memory type.

[0028] An encapsulant 114 surrounds a substantial portion of the high bandwidth memory 112, the RDL no, and the AP die 108. The encapsulant contacts the fanout layer 102 on a first side and has an exposed second side. An optional backside RDL or molding may be mounted or formed on an upper surface of the high bandwidth memory 112 or encapsulant 114. A plurality of conductive posts 116 extend from the fanout layer 102 to the RDL 110 through a portion of the encapsulant 114. A plurality of Through Mold Vias (TMVS) 118 extend between the fanout layer 102 and the exposed second side of the encapsulant 114. The TMVs 118 support communications and power delivery between the fanout layer 102 and Package on Package (POP) memory 120 that provide additional storage resources to the AP die 108. A ball grid array 122 couples to the plurality of TMVs 118 and provides connections between the fanout layer 102 and the POP memory 120. The packaged IC 100 may also include a Printed Circuit Board (PCB) ball grid array 126 coupled to the fanout layer 102 that supports mounting of the packaged IC 100 to a PCB.

[0029] The RDL 110 may include electrical conductors enabling the high bandwidth memory 112 to communicate wirelessly 124 with the AP die 108. With the packaged IC 100 of FIG. 1, a portion of the high bandwidth memory 112 resides outside a footprint of the AP die 108, i.e., the high bandwidth memory 112 overlaps the AP die 108.

[0030] FIG. 2 is a sectional side view illustrating a packaged IC constructed according to a second described embodiment. The packaged IC 200 of FIG. 2 is substantially similar to the packaged IC 100 of FIG. 1 with the addition of a dummy silicon substrate 202 residing beside the high bandwidth memory 112 within the encapsulant 114. The dummy silicon substrate 202 has similar thermal expansion properties as do the high bandwidth memory 112 and the AP die 108 to reduce stress on the packaged IC 200.

[0031] FIG. 3 is a diagrammatic top view of a portion of the packaged IC of FIG. 2. Illustrated in FIG. 2 of the packaged IC 200 are the AP die 108 with the high bandwidth memory 112 and the dummy silicon substrate 202 residing above. The ball grid array 122 is shown but the POP memory 120 is not shown. As illustrated in FIG. 2, a portion of the high bandwidth memory 112 resides outside a footprint of the AP die 108, i.e., the high bandwidth memory 112 overlaps the AP die 108.

[0032] FIG. 4 is a sectional side view illustrating a packaged IC constructed according to a third described embodiment. The packaged IC 400 of FIG. 4 is similar to the packaged IC too of FIG. 1 except that the high bandwidth memory 112 resides within a footprint of the AP die 108.

[0033] FIG. 5 is a sectional side view illustrating a packaged IC constructed according to a fourth described embodiment. The packaged IC 500 of FIG. 5 is similar to the packaged IC 200 of FIG. 2 except that the high bandwidth memory 112 resides within a footprint of the AP die 108. The high bandwidth memory 112 and the dummy silicon substrate 202 are encapsulated into one mold first, with the RDI, 110 outside the high bandwidth memory 112 foot print.

[0034] FIG. 6 is a diagrammatic top view of a portion of the packaged IC of FIG. 5. Illustrated in FIG. 6 are the AP die 108, the high bandwidth memory 112, and the dummy silicon substrate 202 residing above. The ball grid array 122 is also shown but the POP memory 120 is not shown. As illustrated in FIG. 2, a portion of the high bandwidth memory 112 resides outside a footprint of the AP die 108, i.e., the high bandwidth memory 112 overlaps the AP die 108. The high bandwidth memory 112 may reside within a footprint of the AP die 108. The packaged IC 500 may further include a dummy silicon substrate 202 residing beside the high bandwidth memory at least partially within the encapsulant.

[0035] FIG. 7 is a sectional side view illustrating a packaged IC constructed according to a fifth described embodiment. The packaged IC 700 includes elements same/similar to those described previously with reference to FIGS. 1 through 6, which retain common numbering and which may be constructed in a similar fashion as described therewith. The packaged IC 700 of FIG. 7 is shown with additional detail that results from manufacture that may be consistent with the operations 800 of FIG. 8.

[0036] The packaged IC 700 includes a fanout layer 102, the RDL 110, and two distinct mold layers 702 and 704. The first mold layer 702 includes an AP die 108 having a first surface residing substantially adjacent a first surface of the fanout layer 102, a first plurality of TMVs 118A, and conductive posts 116, most/all of which are substantially surrounded by a first encapsulant 114A. The second mold layer 704 includes a high bandwidth memory 112, a dummy silicon substrate 202, and a second plurality of TMVs 118B, most/all of which are substantially surrounded by a second encapsulant 114B. The RDL 110 resides between the first mold layer 702 and the second mold layer 704 and has a first surface coupled to a second surface of the AP die 108. A high bandwidth memory 112 couples to a second surface of the RDL 110 and is configured to communicate wirelessly 124 with the AP die 108.

[0037] As shown in FIG. 7, the high bandwidth memory 112 resides within a footprint of the AP die 108. The packaged IC 700 may further include a dummy silicon substrate 202 residing beside the high bandwidth memory 112 at least partially within the second encapsulant 114B. The packaged IC 700 may also include ball grid arrays 122 and 126 and a POP memory 120.

[0038] FIG. 8 is a flow chart illustrating operations for constructing a packaged IC according to an embodiment of the present disclosure. The operations 800 of FIG. 8 are described with further reference to FIGS. 9A-J, which illustrate the packaged IC during various steps in its construction. Conventional semiconductor manufacturing techniques may be employed with the operations 800 of FIG. 8 to construct the packaged IC. Numbering of FIGS. 9A-J is consistent with the numbering of FIG. 7 (and mostly consistent with the numbering of earlier FIGS.). Operations 800 include first fabricating a second plurality of TMVs 118B on a carrier 902 (step 802, with reference to FIG. 9A). Operations 800 continue with placing a high bandwidth memory die 112 (having a plurality of conductive posts 904) on the carrier 902 (step 804, with reference to FIG. 9B). Step 804 includes optionally also placing a dummy silicon substrate 202 on the earlier 902.

[0039] Operations continue with molding and polishing a second encapsulant 114B to expose the second plurality of TMVs 118B (and a plurality of conductive posts 904 of the high bandwidth memory) (step 806, with reference to FIG. 9C). Operations 800 continue with fabricating an RDL 110 on the second encapsulant 114B that has conductive traces 906 that couple to the conductive posts 904 of the high bandwidth memory 112 (step 808, with reference to FIG. 9D) Step 808 may further include forming TMV extensions that couple to the second plurality of TMVs 118B. Operations 800 then include fabricating a first plurality of TMVs 118A that contact the second plurality of TMV 118B (via the TMV extensions of the RDL 110) (step 810, with reference to FIG. 9E),

[0040] Operations 800 continue with placing an AP die 108 (having short conductors, e.g., copper posts 908) on the RDL 110 (step 812, with reference to FIG. 9F). Operations 800 then continue with molding and polishing a first encapsulant 114A to expose the first plurality of TMVs 118A and the short copper posts 908 of the AP die (step 814, with reference to FIG. 9G),

[0041] Operations 800 continue with fabricating a fanout layer 102 on the first encapsulant 114A having signal conductors 1o6 and power conductors 104 (step 816, with reference to FIG. 9H). Operations 800 continue with optionally forming a ball grid array 126 on the fanout layer 102 (step 818, with reference to FIG. 9I). Operations 800 conclude with demounting the packaged structure from the carrier 902 (and singulated a multi component structure if required) (step 820, with reference to FIG. 9J).

[0042] With the operations 800 of FIG. 8, the RDL 110 may include electrical conductors enabling the high bandwidth memory 112 to communicate wirelessly with the AP die 108. Further, a portion of the high bandwidth memory 112 may reside outside a footprint of the AP die 108 or the high bandwidth memory 112 resides within a footprint of the AP die 108.

[0043] It should be understood at the outset that, although illustrative implementations of one or more embodiments are provided below, the disclosed systems and/or methods may be implemented using any number of techniques, whether currently known or in existence. The disclosure should in 110 way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.

[0044] In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and may be made without departing from the spirit and scope disclosed herein.