SEMICONDUCTOR WAFER AND METHOD OF WAFER THINNING

Abstract

A semiconductor wafer has a base material. The semiconductor wafer may have an edge support ring. A grinding phase of a surface of the semiconductor wafer removes a portion of the base material. The grinder is removed from or lifted off the surface of the semiconductor wafer during a separation phase. The surface of the semiconductor wafer and under the grinder is rinsed during the grinding phase and separation phase to remove particles. A rinsing solution is dispensed from a rinsing solution source to rinse the surface of the semiconductor wafer. The rinsing solution source can move in position while dispensing the rinsing solution to rinse the surface of the semiconductor wafer. The grinding phase and separation phase are repeated during the entire grinding operation, when grinding conductive TSVs, or during the final grinding stages, until the final thickness of the semiconductor wafer is achieved.

Claims

1. A method of thinning a semiconductor wafer, the method comprising: performing a grinding phase on a semiconductor wafer using a grinder; separating the grinder from the semiconductor wafer only along a z axis during a separation phase; and rinsing the semiconductor wafer using a rotating rinsing source during the separation phase.

2. The method of claim 1, further comprising repeating the grinding phase.

3. The method of claim 1, further comprising repeating the grinding phase and the separation phase.

4. The method of claim 1, further comprising separating the grinder 3-10 micrometers from the semiconductor wafer.

5. The method of claim 1, further including reversing rotational movement of the grinder during the separation phase.

6. The method of claim 1, wherein the semiconductor wafer is thinned between 10 and 50 micrometers.

7. A method of thinning a semiconductor wafer, the method comprising: providing a semiconductor wafer including a base material; grinding a surface of the semiconductor wafer during a grinding phase using a grinder to remove a portion of the base material; lifting the grinder off the surface of the semiconductor wafer only in a z axis during a separation phase; and rinsing the surface of the semiconductor wafer using a rotating rinsing source during the separation phase.

8. The method of claim 7, further including repeating the grinding phase and separation phase.

9. The method of claim 7, wherein the rinsing of the semiconductor wafer during the grinding phase and separation phase removes particles.

10. The method of claim 7, wherein the rinsing is continuous.

11. The method of claim 7, wherein the rinsing is pulsed.

12. The method of claim 7, further including reversing movement of the grinder during the separation phase.

13. The method of claim 7, further comprising grinding the surface of the semiconductor wafer during a second grinding phase after the separation phase.

14. A method of thinning a semiconductor wafer, the method comprising: grinding a surface of a semiconductor wafer during a first grinding phase using a grinder to remove a first portion of the semiconductor wafer; lifting the grinder off the surface of the semiconductor wafer only in a z axis during a separation phase; rinsing the semiconductor wafer using a rotating rinsing source during the separation phase; lowering the grinder back to the surface of the semiconductor wafer during the separation phase; and grinding the surface of the semiconductor wafer during a second grinding phase using the grinder to remove a second portion of the semiconductor wafer.

15. The method of claim 14, wherein the separation phase lasts between 3-10 seconds.

16. The method of claim 14, wherein the surface of the semiconductor wafer is rinsed during the first grinding phase, the second grinding phase, and the separation phase.

17. The method of claim 14, wherein the grinder is separated 3-10 micrometers from the surface of the semiconductor wafer during the separation phase.

18. The method of claim 14, further comprising pausing rotational movement of the grinder during the separation phase.

19. The method of claim 14, further comprising reversing rotational movement of the grinder during the separation phase.

20. The method of claim 14, wherein a rotational movement of the grinder during the first grinding phase is opposite a rotational movement of the grinder during the second grinding phase.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIGS. 1a-1c illustrate a semiconductor wafer grinding process leaving cracks, gouges, and other damage in final post-grinding surface;

[0007] FIGS. 2a-2c illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street; and

[0008] FIGS. 3a-3n illustrate a process of wafer thinning using a grinding phase and separation phase to reduce surface damage.

DESCRIPTION

[0009] The following describes one or more embodiments with reference to the figures, in which like numerals represent the same or similar elements. While the figures are described in terms of the best mode for achieving certain objectives, the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

[0010] Semiconductor devices may be manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer may contain active and passive electrical components and optical devices, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions. The optical device detects and records an image by converting the variable attenuation of light waves or electromagnetic radiation into electric signals.

[0011] Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. The wafer is singulated using plasma etching, laser cutting tool, or saw blade along non-functional regions of the wafer called saw streets or scribes. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or interconnect pads for interconnection with other system components. Interconnect pads formed over the semiconductor die are then connected to interconnect pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

[0012] FIG. 2a shows a semiconductor wafer 100 with a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material. A plurality of semiconductor die 104 is formed on wafer 100 separated by non-active saw street 106, as described above. Saw street 106 provides singulation areas to separate semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm) and thickness of 675-775 micrometers (μm). In another embodiment, semiconductor wafer 100 has a width or diameter of 150-300 mm.

[0013] FIG. 2b shows a cross-sectional view of a portion of semiconductor wafer 100. Each semiconductor die 104 has a back surface 108 and an active surface or region 110 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface or region 110 to implement analog circuits or digital circuits, such as digital signal processor (DSP), microcontrollers, ASIC, power conversion, standard logic, amplifiers, clock management, memory, interface circuits, and other signal processing circuit. Semiconductor die 104 may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. Active surface 110 may contain an image sensor area implemented as semiconductor charge-coupled devices (CCD) and active pixel sensors in complementary metal-oxide-semiconductor (CMOS) or N-type metal-oxide-semiconductor (NMOS) technologies. Alternatively, semiconductor die 104 can be an optical lens, detector, vertical cavity surface emitting laser (VCSEL), waveguide, stacked die, electromagnetic (EM) filter, or multi-chip module.

[0014] An electrically conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating process, evaporation, or other suitable metal deposition process. Conductive layer 112 includes one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), tungsten (W), titanium (Ti), titanium tungsten (TiW), or other suitable electrically conductive material. Conductive layer 112 operates as interconnect pads electrically connected to the circuits on active surface 110.

[0015] A plurality of vias is formed through semiconductor wafer 100 using mechanical drilling, laser drilling, or deep reactive ion etching (DRIE). The vias are filled with Al, Cu, Sn, Ni, Au, Ag, W, Ti, TiW, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction conductive through silicon vias (TSV) 114 embedded within semiconductor die 104.

[0016] Semiconductor wafer 100 undergoes electrical testing and inspection as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on semiconductor wafer 100. Software can be used in the automated optical analysis of semiconductor wafer 100. Visual inspection methods may employ equipment such as a scanning electron microscope, high-intensity or ultra-violet light, metallurgical microscope, or optical microscope. Semiconductor wafer 100 is inspected for structural characteristics including warpage, thickness variation, surface particulates, irregularities, cracks, delamination, contamination, and discoloration.

[0017] The active and passive components within semiconductor die 104 undergo testing at the wafer level for electrical performance and circuit function. Each semiconductor die 104 is tested for functionality and electrical parameters, as shown in FIG. 2c, using a test probe head 116 including a plurality of probes or test leads 118, or other testing device. Probes 118 are used to make electrical contact with nodes or conductive layer 112 on each semiconductor die 104 and provide electrical stimuli to interconnect pads 112. Semiconductor die 104 responds to the electrical stimuli, which is measured by computer test system 120 and compared to an expected response to test functionality of the semiconductor die. The electrical tests may include circuit functionality, lead integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, threshold current, leakage current, and operational parameters specific to the component type. The inspection and electrical testing of semiconductor wafer 100 enables semiconductor die 104 that pass to be designated as known good die for use in a semiconductor package.

[0018] FIGS. 3a-3n illustrate a process of wafer thinning using a grinding phase and separation phase to reduce surface damage. FIG. 3a shows an entire area of semiconductor wafer 100 with back surface 108, active surface 110, and conductive TSV 114. Semiconductor die 104 are present in active surface 110, see FIGS. 2a-2c, but not labeled for purposes of the present explanation. Semiconductor wafer 100 has a pre-grinding thickness T.sub.1 of 675-775 μm.

[0019] In FIG. 3b, semiconductor wafer 100 is inverted and mounted with active surface 110 oriented to backgrinding tape 130. In FIG. 3c, the entire back surface 108 undergoes a first grinding operation with grinder or grinding wheel 132 rotating and semiconductor wafer 100 rotating to remove a portion of base substrate material 102. More specifically, grinding wheel 132 is applied to base substrate material 102 at time t.sub.1 and moves in a cyclic, spinning pattern. A small portion of the grinding surface is removed with each pass. The grinding phase leaves particles 135 from base substrate material 102, conductive TSV 114, and grinding wheel 132, and other contaminants on the grinding surface. The particles and contaminants 135 become lodged between grinding wheel teeth 133, and between grinding wheel 132 and the grinding surface. To remove particles and contaminants 135, particularly from under grinding wheel 132, the grinding wheel moves in the z-direction to physically separate the grinding wheel from base substrate material 102. The downward movement of the grinding wheel can be paused instead of reversed, to allow the rinse water to clear the particles.

[0020] FIG. 3d shows grinding wheel 132 lifting off base substrate material 102 at time t.sub.2 during a lift-off or separation phase.

[0021] In FIG. 3e, grinding wheel 132 is again applied to base substrate material 102 during another grinding phase at time t.sub.3. There are typically many cycles of grinding phase and separation phase with a small portion of the grinding surface removed each pass.

[0022] During grinding phase period t.sub.1-t.sub.2 and separation phase period t.sub.2-t.sub.3, rinsing solution source 136 continuously dispenses a rinsing solution or water 138 to the grinding surface to wash away particles and contaminants 135. During separation phase period t.sub.2-t.sub.3, when grinding wheel 132 lifts off the grinding surface, rinsing solution 138 clears most if not substantially all particles and contaminants 135 from under grinding wheel 132 and between grinding wheel teeth 133. The rotation of semiconductor wafer 100 and the volume of rinsing solution 138 disperses particles and contaminants 135 from under grinding wheel 132, between grinding teeth 133, and from the grinding surface.

[0023] Grinding wheel 132 may lift off surface 134 at time t.sub.2, stop rotation, and reverse direction of rotation between time t.sub.2 and time t.sub.3. Grinding wheel 132 may pause in vertical movement during the separation phase, or pause in rotational movement during the grinding phase and/or separation phase. The grinding phase period t.sub.1-t.sub.2 and separation phase period t.sub.2-t.sub.3 repeat during the first backgrinding operation until the desired thickness of semiconductor wafer 100 is achieved. The duration of grinding phase period t.sub.1-t.sub.2 is 5-30 seconds, and the duration of separation phase period t.sub.2-t.sub.3 is 3-10 seconds. In one embodiment, grinding wheel 132 lifts off or moves 3-10 μm in the z-direction away from base substrate material 102, or a sufficient height to clear most if not substantially all particles and contaminants 135 from grinding wheel teeth 133. Rinsing solution 138 washes away particles and contaminants 135 during the separation phase period t.sub.2-t.sub.3, as well as during the grinding phase period t.sub.1-t.sub.2. Alternatively, rinsing solution 138 is applied in pulses to wash away particles and contaminants 135. Rinsing solution source 136 may swivel, rotate, or move about in a pattern over the grinding surface for an even and thorough distribution of rinsing solution 138.

[0024] By lifting grinding wheel 132 from the grinding surface and rinsing away particles and contaminants 135 originating from the grinding operation, either while rotating or paused, the final surface 134 is relatively free of the cracks, gouges, and other damage, as noted in the background. The repeating grinding phase period t.sub.1-t.sub.2 and separation phase period t.sub.2-t.sub.3 may be practiced during the entire grinding operation, when grinding conductive TSVs 114, or during the final grinding stages. Grinding wheel 132 can be designed with a slower wheel wear rate. Semiconductor wafer 100 has a post-grinding thickness T.sub.2 of about 355 μm between active surface 110 and final post-grinding surface 134.

[0025] In another embodiment, grinding wheel 132 may stop rotation, slow down the rotation, or spin slower than normal rate after the grinding phase at time t.sub.2, while the grinding wheel remains on surface 134. Rinsing solution source 136 continuously dispenses a rinsing solution or water 138 to the grinding surface to wash away particles and contaminants 135. At time t.sub.3, grinding wheel 132 re-starts rotation in the previous direction or reverses direction of rotation. The grinding phase and stop phase repeat during the first backgrinding operation until the desired thickness of semiconductor wafer 100 is achieved.

[0026] In FIG. 3f, a second grinding operation is applied to surface 134 with grinder or grinding wheel 140 rotating and semiconductor wafer 100 rotating to remove a portion of base substrate material 102. Grinding wheel 140 moves in a cyclic, spinning pattern across an interior region or wafer grinding area 142 of semiconductor wafer 100. A small portion of the grinding surface is removed with each pass. Grinding wheel 140 is controlled to leave edge support ring 146 of base substrate material 102 around a perimeter of semiconductor wafer 100 for structural support.

[0027] More specifically, grinder or grinding wheel 140 is applied to base substrate material 102 at time t.sub.1, as shown in FIG. 3f. The grinding phase leaves particles 145 from base substrate material 102, conductive TSV 114, and grinding wheel 140, and other contaminants on the grinding surface. The particles and contaminants 145 become lodged between grinding wheel teeth 141, and between grinding wheel 140 and the grinding surface. To remove particles and contaminants 145, particularly from under grinding wheel 140, the grinding wheel moves in the z-direction to physically separate the grinding wheel from base substrate material 102. FIG. 3g shows grinding wheel 140 lifting off base substrate material 102 at time t.sub.2 during a lift-off or separation phase.

[0028] In FIG. 3h, grinding wheel 140 is again applied to base substrate material 102 during another grinding phase at time t.sub.3. There are typically many cycles of grinding phase and separation phase with a small portion of the grinding surface removed each pass.

[0029] During grinding phase period t.sub.1-t.sub.2 and separation phase period t.sub.2-t.sub.3, rinsing solution source 147 continuously dispenses a rinsing solution or water 148 to the grinding surface to wash away particles and contaminants 145. During separation phase t.sub.2-t.sub.3, when grinding wheel 140 lifts off the grinding surface, rinsing solution 148 clears most if not substantially all particles and contaminants 145 from under grinding wheel 140 and between grinding wheel teeth 141. The rotation of semiconductor wafer 100 and the volume of rinsing solution 148 disperses particles and contaminants 145 from under grinding wheel 140, between grinding teeth 141, and from the grinding surface.

[0030] Grinding wheel 140 may lift off surface 144 at time t.sub.2, stop rotation, and reverse direction of rotation between time t.sub.2 and time t.sub.3. Grinding wheel 140 may pause in vertical movement during the separation phase, or pause in rotational movement during the grinding phase and/or separation phase. The grinding phase period t.sub.1-t.sub.2 and separation phase period t.sub.2-t.sub.3 repeat during the second backgrinding operation until the desired thickness of semiconductor wafer 100 is achieved. The duration of grinding phase period t.sub.1-t.sub.2 is 5-30 seconds, and the duration of separation phase period t.sub.2-t.sub.3 is 3-10 seconds. In one embodiment, grinding wheel 140 lifts off or moves 3-10 μm in the z-direction away from base substrate material 102, or a sufficient height to clear most if not substantially all particles and contaminants 145 from grinding wheel teeth 141. Rinsing solution 148 washes away particles and contaminants 145 during the separation phase period t.sub.2-t.sub.3, as well as during the grinding phase period t.sub.1-t.sub.2. Alternatively, rinsing solution 148 is applied in pulses to wash away particles and contaminants 145. Rinsing solution source 147 may swivel, rotate, or move about in a pattern over the grinding surface for an even and thorough distribution of rinsing solution 158.

[0031] By lifting grinding wheel 140 from the grinding surface and rinsing away particles and contaminants 145 originating from the grinding operation, either while rotating or paused, the final surface 144 is relatively free of the cracks, gouges, and other damage, as noted in the background. The repeating grinding phase period t.sub.1-t.sub.2 and separation phase period t.sub.2-t.sub.3 may be practiced during the entire grinding operation, when grinding conductive TSVs 114, or during the final grinding stages. Grinding wheel 140 can be designed with a slower wheel wear rate. In one embodiment, the post-grinding thickness T.sub.3 of semiconductor wafer 100 is 75 μm or less. In another embodiment, the post-grinding thickness T.sub.3 of semiconductor wafer 100 is 10-50 μm.

[0032] In another embodiment, grinding wheel 140 may stop rotation after the grinding phase at time t.sub.2, while the grinding wheel remains on surface 134. Rinsing solution source 147 continuously dispenses a rinsing solution or water 148 to the grinding surface to wash away particles and contaminants 145. At time t.sub.3, grinding wheel 140 re-starts rotation in the previous direction or reverses direction of rotation. The grinding phase and stop phase repeat during the first backgrinding operation until the desired thickness of semiconductor wafer 100 is achieved.

[0033] FIG. 3i shows a top view of grinding wheel 140 removing a portion of surface 134 of semiconductor wafer 100 to reduce the thickness of the semiconductor wafer, and correspondingly semiconductor die 104, in grinding area 142, while leaving edge support ring 146 of base substrate material 102 around a perimeter of the semiconductor wafer. Edge support ring 146 has a width W.sub.146 is 3.0 mm±0.3 mm from inner wall 154 to outer edge 156 of semiconductor wafer 100. The height of edge support ring 146 is the first post-grinding thickness T.sub.2, which is greater than the second post-grinding thickness T.sub.3 of semiconductor wafer 100, to maintain structural integrity of the thinner semiconductor wafer.

[0034] In FIG. 3j, a post-grinding stress relief etch is used to remove or reduce the damage in surface 144 of base substrate material 102 caused by the grinding process. Surface 144 of semiconductor wafer 100 is cleaned with a rinsing solution. An electrically conductive layer 166 is formed over surface 144 using PVD, CVD, electrolytic plating, electroless plating process, evaporation, or other suitable metal deposition process. Conductive layer 166 includes one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, TiW, or other suitable electrically conductive material. Conductive layer 166 provides back-side electrical interconnect for semiconductor die 104. Conductive layer 166 is patterned into electrically common or electrically isolated portions according to the function of semiconductor die 104. Backgrinding tape 130 is removed by exposing the tape to ultraviolet (UV) light and peeling off.

[0035] In FIG. 3k, semiconductor wafer 100 is mounted with active surface 110 oriented to tape portion 170 of film frame 172. In FIG. 3l, edge support ring 146 is removed to be planar with or just above (10-13 μm) conductive layer 172 or surface 144. In FIG. 3m, semiconductor wafer 100 is removed from film frame 172, inverted, and mounted with conductive layer 166 on surface 144 oriented to tape portion 180 of film frame 182. In FIG. 3n, semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool 186 or plasma etch into individual semiconductor die 104.

[0036] While one or more embodiments have been illustrated and described in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present disclosure.