Manufacturing method of low temperature poly-silicon (LTPS) thin film transistor (TFT) substrate and the LTPS TFT substrate

Abstract

The present disclosure relates to a manufacturing method of LTPS TFT substrate and the LTPS TFT substrate. With respect to the manufacturing method, after the gate insulation layer is formed, the gate insulation layer is doped with nitrogen by a plasma containing nitrogen so as to increase the positive charges within the gate insulation layer. As such, the P-type TFT threshold voltage can be negatively shifted so as to enhance the splash screen issue.

Claims

1. A manufacturing method of Low Temperature Poly-silicon (LTPS) thin film transistor (TFT) substrates, comprising: S1: providing a base substrate, and forming a polysilicon active layer on the base substrate; S2: depositing a gate insulation layer on the base substrate and applying a nitrogen doping process using nitrogen-containing plasma toward the gate insulation layer, wherein the gate insulation layer covers the polysilicon active layer; and S3: forming a gate and a source/drain on the gate insulation layer, wherein the gate insulation layer is doped with nitrogen to increase positive charges of the gate insulation layer so as to reduce a threshold voltage of a thin film transistor formed of the polysilicon active layer, the nitrogen-doped gate insulation layer, and the gate and the source/drain.

2. The manufacturing method as claimed in claim 1, wherein the gate insulation layer is a silicon oxide layer.

3. The manufacturing method as claimed in claim 1, wherein in the step S2, at least one of ammonia (NH.sub.3), nitrogen (N.sub.2), and nitrous oxide (NO.sub.2) is selected as a reactive gas in a Plasma Enhanced Chemical Vapor Deposition (PECVD) device so as to produce the nitrogen-containing plasma for the nitrogen doping process being applied to the gate insulation layer; and an electric power used by the PECVD device to perform the nitrogen doping process on the polysilicon active layer is in a range from 2000 to 10000 w, and the nitrogen doping process is applied to the gate insulation layer for a time period ranging from 10 to 120 seconds.

4. The manufacturing method as claimed in claim 3, wherein in the step S2, the ammonia (NH.sub.3) is selected as the reactive gas in the PECVD device so as to produce the nitrogen-containing plasma; and the electric power used by the PECVD device to perform the nitrogen doping process on the polysilicon active layer is in a range from 6000 to 8000 w, and the nitrogen doping process is applied to the gate insulation layer for the time period ranging from 40 to 70 seconds.

5. The manufacturing method as claimed in claim 1, wherein before forming the source/drain, the step S3 further comprises: forming through holes on the gate insulation layer, wherein the through holes corresponds to tops of two ends of the polysilicon active layer, and after the source/drain is formed, the source/drain contact with the polysilicon active layer via the through holes.

6. The manufacturing method as claimed in claim 1, wherein the step S1 or the step S3 further comprises: applying a P-type ion doping to the polysilicon active layer.

7. The manufacturing method as claimed in claim 6, wherein the ions doped during the P-type ion doping are boron ions.

8. A LTPS TFT substrate, comprising: a base substrate, a polysilicon active layer on the base substrate, a gate insulation layer on the base substrate, and a gate and a source/drain on the gate insulation layer, wherein the gate insulation layer covers the polysilicon active layer; and the gate insulation layer being applied with a nitrogen doping process, wherein the gate insulation layer is doped with nitrogen to increase positive charges of the gate insulation layer so as to reduce a threshold voltage of a thin film transistor formed of the polysilicon active layer, the nitrogen-doped gate insulation layer, and the gate and the source/drain.

9. The LTPS TFT substrate as claimed in claim 8, wherein the gate insulation layer is a silicon oxide layer.

10. The LTPS TFT substrate as claimed in claim 8, wherein a P-type ion doping is applied to the polysilicon active layer; through holes corresponds to tops of two ends of the polysilicon active layer are configured on the gate insulation layer, and the source/drain contact with the polysilicon active layer via the through holes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to more clearly illustrate the embodiments of the present invention or prior art, the following figures will be described in the embodiments are briefly introduced. It is obvious that the drawings are merely some embodiments of the present invention, those of ordinary skill in this field can obtain other figures according to these figures without paying the premise.

(2) FIG. 1 is a flowchart illustrating the manufacturing method of the LTPS TFT substrate in accordance with one embodiment of the present disclosure.

(3) FIG. 2 is a schematic view showing the step S1 of the manufacturing method of the LTPS TFT substrate in accordance with one embodiment of the present disclosure.

(4) FIG. 3 is a schematic view showing the step S2 of the manufacturing method of the LTPS TFT substrate in accordance with one embodiment of the present disclosure.

(5) FIG. 4 is a schematic view showing the step S3 of the manufacturing method of the LTPS TFT substrate and the structure of the LTPS TFT substrate in accordance with one embodiment of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(6) The following descriptions for the respective embodiments are specific embodiments capable of being implemented for illustrations of the present invention with referring to appended figures.

(7) FIG. 1 is a flowchart illustrating the manufacturing method of the LTPS TFT substrate in accordance with one embodiment of the present disclosure. The manufacturing method includes the following steps.

(8) In step S1, as shown in FIG. 2, providing a base substrate 10, and forming a polysilicon active layer 30 on the base substrate 10.

(9) In step S2, as shown in FIG. 3, depositing a gate insulation layer 40 on the base substrate 10 and applying a nitrogen doping process using nitrogen-containing plasma toward the gate insulation layer 40, wherein the gate insulation layer 40 covers the polysilicon active layer 30.

(10) In step S3, as shown in FIG. 4, forming a gate 20 and a source/drain 50 on the gate insulation layer 40 to obtain the TFT.

(11) In an embodiment, the gate insulation layer 40 is a silicon oxide layer.

(12) Specifically, in the step S2, at least one of ammonia (NH.sub.3), nitrogen (N.sub.2), and nitrous oxide (NO.sub.2) is used as a reactive gas in a PETCVD (Plasma Enhanced Chemical Vapor Deposition) device so as to produce the nitrogen-containing plasma. With that, the nitrogen doping process is applied to the gate insulation layer 40.

(13) Preferably, in the step S2, ammonia gas is used as a reaction gas to form the nitrogen-containing plasma in the PECVD device.

(14) Specifically, in the step S2, the electric power used by the PECVD device to perform the nitrogen doping process on the polysilicon active layer 30 is 2000-10000 w. In an example, the electric power may be 6000-8000 w. The nitrogen doping process may be applied to the gate insulation layer 40 for a period ranging from 10 to 120 seconds. In another example, the nitrogen doping process may be applied to the gate insulation layer 40 for a period ranging from 40 to 70 seconds.

(15) In one embodiment, before forming the source/drain 50, the step S3 further includes: forming through holes 45 on the gate insulation layer 40, wherein the through holes 45 corresponds to tops of two ends of the polysilicon active layer 30. After the source/drain 50 is formed, the source/drain 50 contact with the polysilicon active layer 30 via the through holes 45.

(16) In an example, the step S1 or the step S3 further includes: applying a P-type ion doping on the polysilicon active layer 30 so as to form the P-type TFT structure.

(17) In an example, the ions doped during the P-type ion doping are boron ions.

(18) The present disclosure verifies the technical effects by the following experiments:

First Experiment

(19) Using NH.sub.3 and N.sub.2 as reaction gases to form a nitrogen-containing plasma in the PECVD device. The gate insulation layer 40 of the silicon oxide layer is subjected to the nitrogen doping process. The electric power used in the PECVD device is 6000 W, and the time period of the nitrogen doping process is 55 seconds. The result is a negative shift of the P-Vth, and the P-Vth distribution interval is −2.61 to −1.31V.

Second Experiment

(20) Using NH.sub.3 and N.sub.2 as reaction gases to form a nitrogen-containing plasma in the PECVD device. The gate insulation layer 40 of the silicon oxide layer is subjected to the nitrogen doping process. The electric power used in the PECVD device is 7000 W, and the time period of the nitrogen doping process is 55 seconds. The result is a negative shift of the P-Vth, and the P-Vth distribution interval is −2.48 to −1.23V.

Third Experiment

(21) Using NH.sub.3 and N.sub.2 as reaction gases to form a nitrogen-containing plasma in the PECVD device. The gate insulation layer 40 of the silicon oxide layer is subjected to the nitrogen doping process. The electric power used in the PECVD device is 8000 W, and the time period of the nitrogen doping process is 55 seconds. The result is a negative shift of the P-Vth, and the P-Vth distribution interval is −2.8 to −1.39V.

(22) It can be concluded from the above experiments that the present disclosure has the effect of negatively shifting the threshold voltage of the P-type TFT, and the maximum value of the threshold voltage of the P-type TFT can be reduced from −1V to −1.3V, when being compared with the prior art. Therefore, the present disclosure may also achieve the effect of reducing the threshold voltage of the N-type TFT.

(23) With respect to the manufacturing method of the LTPS TFT substrate, after the gate insulation layer 40 is formed, the gate insulation layer 40 is doped with a nitrogen-containing plasma to increase the positive charge in the gate insulation layer 40. Therefore, the P-type TFT threshold voltage can be negatively shifted, and the maximum value of the P-type TFT threshold voltage can be reduced from −1 V to −1.3 V, when being compared with the prior art, thereby improving the splash screen issue.

(24) FIG. 4 is a schematic view showing the step S3 of the manufacturing method of the LTPS TFT substrate and the structure of the LTPS TFT substrate in accordance with one embodiment of the present disclosure. The LTPS TFT substrate includes a base substrate base substrate 10, a polysilicon active layer 30 on the base substrate 10, a gate insulation layer 40 on the base substrate 10, and a gate 20 and a source/drain 50 on the gate insulation layer 40, wherein the gate insulation layer 40 covers the polysilicon active layer 30.

(25) The gate insulation layer 40 of the silicon oxide layer is subjected to the nitrogen doping process.

(26) In an embodiment, the gate insulation layer 40 is a silicon oxide layer.

(27) In an embodiment, the polysilicon active layer 30 is subjected to the P-type doping process. The through holes 45 are formed on the gate insulation layer 40, wherein the through holes 45 corresponds to tops of two ends of the polysilicon active layer 30. The source/drain 50 contact with the polysilicon active layer 30 via the through holes 45.

(28) After the gate insulation layer 40 is applied with the nitrogen doping process, the threshold voltage of the P-type TFT may be negatively shifted, and the maximum value of the threshold voltage of the P-type TFT can be reduced from −1V to −1.3V, when being compared with the prior art. Therefore, the present disclosure may also enhance the splash screen issue.

(29) In view of the above, after the gate insulation layer is formed, the gate insulation layer is doped with nitrogen by a plasma containing nitrogen so as to increase the positive charges within the gate insulation layer. As such, the P-type TFT threshold voltage can be negatively shifted. Compared with the convention technology, the maximum value of the P-type TFT threshold voltage can be reduced from −1 V to −1.3 V, thereby improving the splash screen issue. With respect to the LTPS TFT substrate, the gate insulation layer is subjected to the nitrogen-doping process, thereby enabling the P-type TFT threshold voltage to be negatively shifted, and the maximum value of the P-type TFT threshold voltage can be reduced from −1 V to −1.3 V, when being compared to the conventional technology. In turn, the splash screen issue of the display panel can be improved.

(30) Above are embodiments of the present invention, which does not limit the scope of the present invention. Any equivalent amendments within the spirit and principles of the embodiment described above should be covered by the protected scope of the invention.