Array substrate, manufacturing method thereof and display device using the same

Abstract

The present disclosure relates to an array substrate, manufacturing method thereof and display device using the same. The method for manufacturing the array substrate includes: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer in one deposition process; and processing the amorphous silicon layer to transform the amorphous silicon layer into a polysilicon layer. Through the above-mentioned method, the present disclosure can solve the problem of affecting the concentration of current carriers that caused by the oxidation of the surface of polysilicon, and improve the performance of the array substrate.

Claims

1. A method for manufacturing a display device, comprising providing an array substrate comprising a polysilicon layer and insulating layer being disposed in a stacked manner; introducing a first mixed gas to deposit an amorphous silicon layer; introducing a second mixed gas to deposit the insulating layer on the amorphous silicon layer, wherein the insulating layer covers the amorphous silicon layer, the second mixed gas is a mixed gas of SiH.sub.4 and NH.sub.3; dehydrogenating the amorphous silicon layer; and performing an excimer laser annealing process on the dehydrogenated amorphous silicon layer to transform the amorphous silicon layer into the polysilicon layer while the insulating layer is covering the amorphous silicon layer; wherein, an amorphous silicon layer and an insulating layer covering the amorphous silicon layer are formed during performing one same process of chemical vapor deposition (CVD), the polysilicon layer has a first side face and a second side face, the insulating layer has a third side face and a fourth side face, the first side face is flushed with the third side face, and the second side face is flushed with the fourth side face.

2. The device of claim 1, wherein the first mixed gas is a mixed gas of SiH.sub.4 and H.sub.2.

3. The device of claim 1, wherein the array substrate further comprises a substrate and buffer layer being disposed in a stacked manner, and the polysilicon layer is disposed on the buffer layer.

4. The device of claim 3, wherein the array substrate further comprises a gate electrode formed on the insulating layer, a dielectric layer formed on the insulating layer and the gate electrode, and a source electrode and a drain electrode formed on the dielectric layer; wherein the source electrode and the drain electrode are respectively connected to the polysilicon layer through a through hole formed on the dielectric layer and the insulating layer.

5. The device of claim 4, wherein: the gate electrode is made of metal Mo; or the source electrode and the drain electrode are respectively composed of metal Ti, metal Al, and metal Ti being disposed in a stacked manner.

6. A method for manufacturing an array substrate, comprising: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer during performing one same process of CVD, wherein the insulating layer covers the amorphous silicon layer; and processing the amorphous silicon layer to transform the amorphous silicon layer into a polysilicon layer while the insulating layer is covering the amorphous silicon layer wherein the polysilicon layer has a first side face and a second side face, the insulating layer has a third side face and a fourth side face, the first side face is flushed with the third side face, and the second side face is flushed with the fourth side face; wherein the forming the amorphous silicon layer and the insulating layer covering the amorphous silicon layer comprises: introducing a first mixed gas to deposit the amorphous silicon layer; and introducing a second mixed gas to deposit the insulating layer on the amorphous silicon layer, wherein the second mixed gas is a mixed gas of SiH.sub.4 and NH.sub.3.

7. The method of claim 6, wherein the first mixed gas is a mixed gas of SiH.sub.4 and H.sub.2.

8. The method of claim 6, wherein the processing the amorphous silicon layer to transform the amorphous silicon layer into the polysilicon layer comprises: dehydrogenating the amorphous silicon layer; and performing an excimer laser annealing process on the dehydrogenated amorphous silicon layer to transform the amorphous silicon layer into the polysilicon layer.

9. The method of claim 6, before the forming the amorphous silicon layer and the insulating layer covering the amorphous silicon layer in one deposition process further comprising: providing a substrate; and forming a buffer layer on the substrate; the forming the amorphous silicon layer and the insulating layer covering the amorphous silicon layer in one deposition process comprises: forming the amorphous silicon layer and the insulating layer covering the amorphous silicon layer on the buffer layer in one deposition process.

10. The method of claim 9, after the processing the amorphous silicon layer to transform the amorphous silicon layer into the polysilicon layer further comprising: forming a gate electrode on the insulating layer; forming a dielectric layer on the insulating layer and the gate electrode; forming a through hole on the dielectric layer and the insulating layer so that the polysilicon layer is partially exposed; and forming a source electrode and a drain electrode on the dielectric layer, wherein the source electrode and the drain electrode are respectively connected to the polysilicon layer through the through hole.

11. The method of claim 10, wherein: the gate electrode is made of metal Mo; or the source electrode and the drain electrode are respectively composed of metal Ti, metal Al, and metal Ti being disposed in a stacked manner.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to more clearly illustrate the technical solution in the embodiments of the present disclosure, the accompanying drawings to be used in the description of the embodiments are briefly described below. It will be apparent that the accompanying drawings in the following description are merely embodiments of the present disclosure, and other accompanying drawings may be obtained without creative work for those skilled in the art.

(2) FIG. 1 is a schematic diagram of the structure of an array substrate in the prior art.

(3) FIG. 2 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.

(4) FIG. 3 is a schematic diagram of the structure manufactured by block 22 of the method for manufacturing the array substrate according to the embodiment of the present disclosure.

(5) FIG. 4 is a flow chart of a method for manufacturing an array substrate according to another embodiment of the present disclosure.

(6) FIG. 5 is a flow chart of a method for manufacturing an array substrate according to still another embodiment of the present disclosure.

(7) FIG. 6 is a schematic diagram of the structure manufactured by blocks 51-53 of the method for manufacturing the array substrate according to the still another embodiment of the present disclosure.

(8) FIG. 7 is a schematic diagram of the structure manufactured by block 54 of the method for manufacturing the array substrate according to the still another embodiment of the present disclosure.

(9) FIG. 8 is a schematic diagram of the structure manufactured by blocks 55-57 of the method for manufacturing the array substrate according to the still another embodiment of the present disclosure.

(10) FIG. 9 is a schematic diagram of the structure manufactured by block 58 of the method for manufacturing the array substrate according to the still another embodiment of the present disclosure.

(11) FIG. 10 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure.

(12) FIG. 11 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

(13) The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are only used to explain the present disclosure and are not intended to limit the present disclosure. It should also be noted that for ease of description, only part but not all of the structures related to the present disclosure are shown in the drawings. All other embodiments obtained based on the embodiments of the present disclosure by those skilled in the art without making creative efforts shall fall within the protection scope of the present disclosure.

(14) The terms “first”, “second”, and the like in the present disclosure are used to distinguish different objects and are not used to describe a specific sequence. Furthermore, the terms “include” and “have” and any variants thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of blocks or units is not limited to the listed blocks or units, but may optionally include blocks or units that are not listed, or may optionally further include other blocks or units inherent to these processes, methods, products, or devices.

(15) An “embodiment” mentioned herein means that a particular feature, structure, or characteristic described with reference to the embodiment can be included in at least one embodiment of the present disclosure. The appearance of the word in various places in the specification is not necessarily all referring to the same embodiment, nor is an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art, both explicitly and implicitly, that the embodiments described herein can be combined with other embodiments.

(16) Referring to FIG. 1, a schematic diagram of the structure of an array substrate in the prior art is depicted.

(17) Taking a top-gate type array substrate in the prior art as an example, the top-gate array substrate includes a polysilicon layer 13, an insulating layer 14, and a gate electrode 15 which are disposed in a stacked manner.

(18) Since in the process of fabricating the polysilicon layer 13, a layer of amorphous silicon is generally deposited first, and a polysilicon layer 13 is formed after the amorphous silicon layer is processed. Before the insulating layer 14 is formed, the polysilicon layer 13 is exposed to air, and the surface of the polysilicon layer 13 is oxidized in the air to form a thin (about 5 nm) impurity layer 13a. The impurity layer 13a generally includes SiO.sub.x which has many defects. The impurity layer 13a is between the polysilicon layer 13 and the insulating layer 14, which will catch carriers and change the concentration of the current carriers when a TFT is in operation, and the performance of the TFT is largely affected.

(19) Referring to FIG. 2, a flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure is depicted. The method may include the following blocks.

(20) At block 21: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer in one deposition process.

(21) Amorphous silicon is a form of elemental silicon with brownish black or grayish black microcrystals, and does not have complete diamond cells while does not have high purity. Its melting point, density and hardness are also significantly lower than crystalline silicon. Its chemical property is more active than crystalline silicon, and it can be produced by reducing silicon tetrahalide through heating an active metal (e.g., sodium or potassium), or by reducing silica with a reducing agent such as carbon. An amorphous silicon thin film which contains hydrogen can be produced by using the glow discharge vapor deposition method.

(22) The insulating layer may use SiO.sub.x, SiN.sub.x, or a mixture of SiO.sub.x and SiN.sub.x.

(23) It can be understood that the above-mentioned deposition process can be performed by physical vapor deposition (PVD) or chemical vapor deposition (CVD), for example, gas evaporation.

(24) At block 22: processing the amorphous silicon layer to transform the amorphous silicon layer into a polysilicon layer.

(25) Optionally, in this embodiment, excimer laser annealing (ELA) technology is mainly used to transform amorphous silicon into polysilicon.

(26) The temperature at which using ELA to prepare p-Si material is usually below 450° C., and ordinary TFT glass can be used. The p-Si material obtained by this method completely meets the performance requirements of pixel TFT switching devices and peripheral driving TFT devices. Because an XeCl (hafnium chloride) excimer laser apparatus has good gas stability and the a-Si film has a high absorption coefficient (approximately 106 cm.sup.−1) at a wavelength of 308 nm, the XeCl excimer laser apparatus is generally used for production. The a-Si film was initially annealed by using a spotted laser beam, which is very slow and the obtained p-Si material has many defects. If the laser beam is changed into the laser line, the laser scanning process will become simpler.

(27) Referring to FIG. 3, a schematic diagram of the structure manufactured by block 22 of the method for manufacturing the array substrate according to the embodiment of the present disclosure is depicted. An amorphous silicon layer 12 and the insulating layer 14 covering the amorphous silicon layer 12 are formed in one deposition process first, and then the amorphous silicon layer 12 is subjected to an excimer laser annealing process to transform the amorphous silicon layer 12 into the polysilicon layer 13.

(28) Different from the prior art, the method for manufacturing the array substrate in this embodiment includes: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer in one deposition process; and processing the amorphous silicon layer to transform the amorphous silicon layer into a polysilicon layer. By means of the above-mentioned methods, on the one hand, the problem that the polysilicon is exposed to air and oxidized after the amorphous silicon is transformed into the polysilicon is avoided, which solves the problem of affecting the concentration of current carriers that caused by the oxidation of the surface of polysilicon, and improves the performance of the array substrate. On the other hand, the amorphous silicon and the insulating layer are formed in the same process, which reduces the number of processes and saves the manufacturing time and costs.

(29) Referring to FIG. 4, a flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure is depicted. The method may include the following blocks.

(30) At block 41: introducing a first mixed gas to deposit the amorphous silicon layer.

(31) At block 42: introducing a second mixed gas to deposit the insulating layer on the amorphous silicon layer.

(32) The insulating layer may be SiN.sub.x. Specifically, the first mixed gas may be a mixed gas of SiH.sub.4 and H.sub.2, and the second mixed gas may be a mixed gas of SiH.sub.4 and NH.sub.3.

(33) Specifically, a-Si and SiN.sub.x can be deposited at one time by using CVD technology, that is, two blocks are used in a CVD process. The gas in the first block is SiH.sub.4+H.sub.2, and the second block is to replace the gas with SiH.sub.4+NH.sub.3. Consequently, a-Si and SiN.sub.x can be formed by using CVD technology once.

(34) At block 43: dehydrogenating the amorphous silicon layer.

(35) At block 44: performing an excimer laser annealing process on the dehydrogenated amorphous silicon layer to transform the amorphous silicon layer into the polysilicon layer.

(36) Specifically, a-Si is transformed into p-Si by ELA after performing a dehydrogenation process on a-Si, while SiN.sub.x has been formed and will not be affected. A p-Si polysilicon layer and a gate insulating layer SiN.sub.x are formed by using CVD method once.

(37) In the following, a top-gate TFT is used as an example to describe its manufacturing method in detail.

(38) Referring to FIG. 5, a flow chart of a method for manufacturing an array substrate according to still another embodiment of the present disclosure is depicted. The method may include the following blocks.

(39) At block 51: providing a substrate.

(40) The substrate may be a glass substrate or a plastic substrate. It can be understood that the substrate is only used as a substrate during the manufacturing process, and the substrate is peeled off after the array substrate is manufactured.

(41) It can be understood that PVD or CVD can be used in the production of each functional layer described below, for example, gas evaporation. If the formed functional layer needs a corresponding patterning process, photolithography, development, etching, peeling, and the like may be used, which will not be described below.

(42) At block 52: forming an insulating layer on the substrate.

(43) The insulating layer may be SiO.sub.x, SiN.sub.x or a mixture of SiO.sub.x and SiN.sub.x.

(44) At block 53: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer on the insulating layer in one deposition process.

(45) Referring to FIG. 6, a schematic diagram of the structure manufactured by blocks 51-53 of the method for manufacturing the array substrate according to the still another embodiment of the present disclosure is depicted. As shown in FIG. 6, a substrate 10 is provided, a buffer layer 11 is formed on the substrate 10, and an amorphous silicon layer 12 and an insulating layer 14 covering the amorphous silicon layer 12 are formed on the buffer layer 11 in one deposition process.

(46) Specifically, a-Si and SiN.sub.x can be deposited at one time by using CVD technology. That is, two blocks are used in a CVD process. The gas in the first block is SiH.sub.4+H.sub.2, and the second block is to replace the gas with SiH.sub.4+NH.sub.3. Consequently, a-Si and SiN.sub.x can be formed by using CVD technology once.

(47) At block 54: processing the amorphous silicon layer to transform the amorphous silicon layer into a polysilicon layer.

(48) Referring to FIG. 6 and FIG. 7 simultaneously, FIG. 7 is a schematic diagram of the structure manufactured by block 54 of the method for manufacturing the array substrate according to the still another embodiment of the present disclosure. The amorphous silicon layer 12 is processed so that the amorphous silicon layer 12 becomes a polysilicon layer 13.

(49) Specifically, a-Si is transformed into p-Si by ELA after performing a dehydrogenation process on a-Si, while SiN.sub.x has been formed and will not be affected. A p-Si polysilicon layer and a gate insulating layer SiN.sub.x are formed by using CVD method once.

(50) At block 55: forming a gate electrode on the insulating layer.

(51) At block 56: forming a dielectric layer on the insulating layer and the gate electrode.

(52) At block 57: forming a through hole on the dielectric layer and the insulating layer so that the polysilicon layer is partially exposed.

(53) Referring to FIG. 8, a schematic diagram of the structure manufactured by blocks 55-57 of the method for manufacturing the array substrate according to the still another embodiment of the present disclosure is depicted. A gate electrode 15 is formed on the insulating layer 14, a dielectric layer 16 is formed on the insulating layer 14 and the gate electrode 15, and a through hole is formed on the dielectric layer 16 and the insulating layer 14 so that the polysilicon layer 13 is partially exposed.

(54) It can be understood that the gate electrode 15 may be formed by depositing a conductive layer first, and then forming the gate electrode 15 through a patterning process. Therefore, the gate electrode 15 does not completely cover the insulating layer 14. Hence, when forming the trough hole on the dielectric layer 16 and the insulating layer 14. The trough hole is formed at a position where the gate electrode 15 is not covered, and the through hole will not contact with the gate electrode 15.

(55) The gate electrode 15 is composed of metal Mo, and the dielectric layer 16 composes of SiO.sub.x, SiN.sub.x or a mixture of SiO.sub.x and SiN.sub.x.

(56) At block 58: forming a source electrode and a drain electrode on the dielectric layer, where the source electrode and the drain electrode are respectively connected to the polysilicon layer through the through hole.

(57) Referring to FIG. 9, a schematic diagram of the structure manufactured by block 58 of the method for manufacturing the array substrate according to the still another embodiment of the present disclosure is depicted. A source electrode 171 and a drain electrode 172 are formed on the dielectric layer 16, and the source electrode 171 and the drain electrode 172 are respectively connected to the polysilicon layer 13 through the through hole.

(58) The source electrode 171 and the drain electrode 172 are composed of metal Ti, metal Al, and metal Ti which are disposed in a stacked manner.

(59) It can be understood that the array substrate in this embodiment may also be a bottom-gate type array substrate, that is, the layers on the substrate 10 are sequentially stacked in the following order: the buffer layer 11, the gate electrode 15, the gate insulating layer 14, the polysilicon layer 13, and the dielectric layer 16, and the source electrode 171 and the drain electrode 172 are respectively connected to the polysilicon layer 13 through the through hole formed on the dielectric layer 16 and the insulating layer 14.

(60) Referring to FIG. 10, a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure is depicted. The array substrate includes a substrate 10, a buffer layer 11, a polysilicon layer 13, an insulating layer 14, a gate 15, a dielectric layer 16, a source electrode 171 and a drain electrode 172 which are disposed in a stacked manner. In which, the source electrode 171 and the drain electrode 172 are respectively connected to the polysilicon layer 13 through the through hole formed on the dielectric layer 16 and the insulating layer 14.

(61) The method for manufacturing the polysilicon layer 13 and the insulating layer 14 is as follows: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer on the insulating layer in one deposition process; and processing the amorphous silicon layer to transform the amorphous silicon layer into a polysilicon layer.

(62) Specifically, a-Si and SiN.sub.x can be deposited at one time by using CVD technology. That is, two blocks are used in a CVD process. The gas in the first block is SiH.sub.4+H.sub.2, and the second block is to replace the gas with SiH.sub.4+NH.sub.3. Consequently, a-Si and SiN.sub.x can be formed by using CVD technology once. a-Si is transformed into p-Si by ELA (excimer laser annealing) after performing a dehydrogenation process on a-Si, while SiN.sub.x has been formed and will not be affected. A p-Si polysilicon layer and a gate insulating layer SiN.sub.x are formed by using CVD method once.

(63) It can be understood that the array substrate of this embodiment can be manufactured using the manufacturing method provided in the above-mentioned embodiments, which will not be described here.

(64) Referring to FIG. 11, a schematic diagram of the structure of a display device according to an embodiment of the present disclosure is depicted. The display device 110 includes a display panel 111. The display panel 111 includes an array substrate.

(65) The display panel 111 may be a liquid crystal panel or an OLED panel, that is, the array substrate provided by the above-mentioned embodiments may be applied to a liquid crystal panel or an OLED panel.

(66) Also referring to FIG. 10, if the display panel 111 is applied to a liquid crystal panel, a flat layer may be further disposed on the source electrode 171, the drain electrode 172, and the dielectric layer 16. A common electrode is disposed on the flat layer, and the common electrode connects the source electrode 171 or the drain electrode 172 through a through hole on the flat layer. In addition, the liquid crystal panel further includes a color filter substrate disposed opposite to the array substrate, the color filter substrate may include a color filter and a pixel electrode, and the array substrate and the color filter substrate form the liquid crystal panel after a pair box process.

(67) Also referring to FIG. 10, if the display panel 111 is applied to an OLED panel, a flat layer may be further disposed on the source electrode 171, the drain electrode 172, and the dielectric layer 16, and an anode, an OLED light emitting material, a cathode, and an encapsulation layer may be sequentially stacked on the flat layer. In which, the anode is connected to the source 171 electrode or the drain electrode 172 through a through hole on the flat layer.

(68) Different from the prior art, when making the polysilicon layer in the array substrate and the display device using the array substrate provided in this embodiment, the amorphous silicon layer and the insulating layer covering the amorphous silicon layer are formed in one deposition process; and then the amorphous silicon layer is processed to transform the amorphous silicon layer into a polysilicon layer. On the one hand, the problem that the polysilicon is exposed to air and oxidized after the amorphous silicon is transformed into the polysilicon is avoided, which solves the problem of affecting the concentration of current carriers that caused by the oxidation of the surface of polysilicon, and improves the performance of the array substrate. On the other hand, the amorphous silicon and the insulating layer are formed in the same process, which reduces the number of processes and saves the manufacturing time and it is beneficial to reduce the manufacturing cost of the display device.

(69) The foregoing descriptions are merely implementation manners of the present disclosure, while do not limit the scope of the present disclosure. Any equivalent structure or equivalent process change using the description of the present disclosure and the accompanying drawings, and direct or indirect applications in other related technical fields, are all within the protection scope of the present disclosure.