Managed substrate effects for stabilized SOI FETs

Abstract

Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

Claims

1. An integrated circuit structure including: (a) a high resistivity silicon substrate; (b) a layer that includes at least one trap rich region and at least one non-trap rich region formed on the substrate; (c) an insulator layer formed on the layer that includes at least one trap rich region and at least one non-trap rich region; (d) an active layer formed on the insulator layer; (e) first circuitry fabricated in and/or on the active layer above at least one non-trap rich region, the first circuitry including circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry; and (f) second circuitry fabricated in and/or on the active layer above the at least one trap rich layer, the second circuitry including circuitry that can benefit from the characteristics of the trap rich layer.

2. The invention of claim 1, wherein the layer that includes at least one trap rich region and at least one non-trap rich region is formed from a layer of non-trap rich material on the substrate that has been masked and etched through to the substrate to define at least one region in which trap rich material is to be formed, and wherein trap rich material is formed within at least one such region to define the at least one trap rich region.

3. The invention of claim 1, wherein the layer that includes at least one trap rich region and at least one non-trap rich region is formed from a layer of trap rich material on the substrate that has been masked and etched through to the substrate to define the at least one non-trap rich region.

4. The invention of claim 3, wherein a filler material is formed within each non-trap rich region before the insulator layer is formed on the layer that includes at least one trap rich region and at least one non-trap rich region.

5. The invention of claim 1, wherein the layer that includes at least one trap rich region and at least one non-trap rich region is formed on the substrate that has been masked to define at least one region in which trap rich material is to be formed, and wherein trap rich material is formed within at least one such region to define the at least one trap rich region.

6. The invention of claim 5, wherein a filler material is formed on the substrate surrounding the at least one trap rich region to define the at least one non-trap rich region.

7. The invention of claim 1, further including at least one substrate contact near at least one area of circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry.

8. An integrated circuit structure including: (a) a high resistivity silicon substrate; (b) a trap rich layer formed on the substrate; (c) at least one modified region formed within the trap rich layer that is more conductive than the trap rich layer; (d) an insulator layer formed on the trap rich layer; (e) an active layer formed on the insulator layer; (f) first circuitry fabricated in and/or on the active layer above at least one modified region; and (g) second circuitry fabricated in and/or on the active layer above the trap rich layer but not above any modified region.

9. The invention of claim 8, wherein each modified region is formed by implanting or diffusing a dopant into a selected area of the trap rich layer before the insulator layer is formed on the trap rich layer.

10. The invention of claim 8, wherein each modified region is formed by implanting a dopant into a selected area of the trap rich layer after the insulator layer is formed on the trap rich layer.

11. The invention of claim 8, wherein each modified region is formed by laser annealing a selected area of the trap rich layer after the insulator layer is formed on the trap rich layer.

12. The invention of claim 8, wherein each modified region is formed by implanting a dopant into a selected area of the trap rich layer after forming the active layer.

13. The invention of claim 8, wherein each modified region is formed by laser annealing a selected area of the trap rich layer after forming the active layer.

14. The invention of claim 8, further including at least one substrate contact formed near the first circuitry.

15. The invention of claim 8, wherein the first circuitry includes circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry in the absence of at least one of the modified regions.

16. The invention of claim 8, wherein the second circuitry includes circuitry that can benefit from the characteristics of the trap rich layer.

17. An integrated circuit structure formed from a silicon-on-insulator (SOI) substrate having a trap rich layer formed on the substrate, an insulator layer formed on the trap rich layer, and an active layer formed on the insulator layer, wherein a void is formed through the active layer, the underlying insulator layer, and the underlying trap rich layer to the substrate to define at least one non-trap rich region, wherein first transistor circuitry is fabricated above one of the non-trap rich regions, and wherein second transistor circuitry is fabricated above the trap rich layer.

18. The invention of claim 17, wherein the first transistor circuitry includes circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry.

19. The invention of claim 17, wherein the second transistor circuitry includes circuitry that can benefit from the characteristics of the trap rich layer.

20. The invention of claim 18, further including an epitaxial material formed on the substrate within the void, interposed between the substrate and the first transistor circuitry.

21. An integrated circuit structure formed from a silicon-on-insulator (SOI) substrate having a trap rich layer formed on the substrate, an insulator layer formed on the trap rich layer, an active layer formed on the insulator layer, and at least one raised semiconductor region formed on the active layer, wherein first circuitry is fabricated on or in at least one of the raised semiconductor regions, and second circuitry is fabricated in and/or on the active layer above the trap rich layer.

22. The invention of claim 21, wherein the first circuitry includes circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry.

23. The invention of claim 21, wherein the second circuitry includes circuitry that can benefit from the characteristics of the trap rich layer.

Description

DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram of a typical prior art transceiver such as the type that might be used in a cellular telephone.

(2) FIG. 2 is a block diagram of a prior art bias voltage generation circuit.

(3) FIG. 3 is block diagram showing a typical prior art SOI IC structure for a single FET.

(4) FIG. 4 is block diagram showing an improved prior art SOI IC structure for a single FET.

(5) FIG. 5A is a block diagram showing an in-process step in the manufacture of an SOI wafer having a high resistivity substrate.

(6) FIG. 5B is a block diagram of an SOI wafer processed in accordance with the teachings of FIG. 5A.

(7) FIG. 6A is a block diagram showing an in-process step in the manufacture of an SOI wafer having a high resistivity substrate and a trap rich layer.

(8) FIG. 6B is a block diagram of an SOI wafer processed in accordance with the teachings of FIG. 6A.

(9) FIG. 7A is a block diagram showing an in-process step in the manufacture of an SOI wafer having a high resistivity substrate, a trap rich layer, and a BOX insulator layer.

(10) FIG. 7B is a block diagram of an SOI wafer processed in accordance with the teachings of FIG. 7A.

(11) FIG. 7C is a block diagram showing a variant in-process step in the manufacture of an SOI wafer having a high resistivity substrate, a trap rich layer, a BOX insulator layer, and an active layer.

(12) FIG. 8A is a block diagram showing an in-process step in the manufacture of an SOI wafer having a high resistivity substrate, a trap rich layer, and a BOX insulator layer.

(13) FIG. 8B is a block diagram of an SOI wafer processed in accordance with the teachings of FIG. 8A.

(14) FIG. 8C is a block diagram showing a variant in-process step in the manufacture of an SOI wafer having a high resistivity substrate, a trap rich layer, a BOX insulator layer, and an active layer.

(15) FIG. 9A is a block diagram of a fabricated SOI wafer.

(16) FIG. 9B is a block diagram of an etched fabricated SOI wafer.

(17) FIG. 9C is a block diagram of an etched SOI wafer processed in accordance with the teachings of FIG. 9B.

(18) FIG. 9D is a block diagram of a variant of an etched SOI wafer processed in accordance with the teachings of FIG. 9B.

(19) FIG. 10A is a block diagram of a fabricated SOI wafer.

(20) FIG. 10B is a block diagram of an augmented SOI wafer.

(21) FIG. 10C is a block diagram of an augmented SOI wafer processed in accordance with the teachings of FIG. 10B.

(22) FIG. 11 is block diagram showing an SOI IC structure with a trap rich layer and substrate contacts for a single FET.

(23) FIG. 12 is a top plan view of an area of a stylized IC that includes twelve example circuits of a type susceptible to accumulated charge resulting from the interaction of an unmodified trap rich layer and transient changes of state of FETs comprising such circuitry (e.g., current mirrors for bias circuits of a power amplifier).

(24) FIG. 13 is a top plan view of an area of a stylized IC that includes the twelve example circuits of FIG. 12 surrounded by a plurality of S-contacts.

(25) FIG. 14 is block diagram showing an SOI IC structure with a trap rich layer, a BOX insulator layer, and substrate contacts for a single FET.

(26) FIG. 15 is a process flow diagram showing a first method for forming a silicon-on-insulator (SOI) integrated circuit on a high resistivity substrate.

(27) FIG. 16 is a process flow diagram showing a second method for forming a silicon-on-insulator (SOI) integrated circuit on a high resistivity substrate.

(28) FIG. 17 is a process flow diagram showing a third method for forming a silicon-on-insulator (SOI) integrated circuit on a high resistivity substrate.

(29) FIG. 18 is a process flow diagram showing a fourth method for forming a silicon-on-insulator (SOI) integrated circuit on a high resistivity substrate.

(30) Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

(31) The invention encompasses several types of modifications in selected regions to silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates.

(32) In specific applications, use of one or more embodiments of the present invention lowers standby power consumption of FETs while enabling a very quick sleep-to-active transition time (e.g., <1 μS) and achieving a very stable gain very soon after becoming active.

(33) Accordingly, embodiments of the present invention retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

(34) Modification of Trap Rich Layer During Formation

(35) In a first embodiment, a trap rich layer is selectively formed on a high resistivity substrate.

(36) FIG. 5A is a block diagram showing an in-process step in the manufacture of an SOI wafer 500 having a high resistivity substrate 402. In this example, a mask is used to define a trap rich region 502 on the high resistivity substrate 402 (shown truncated vertically, the actual proportions would more typically resemble FIG. 4). The trap rich region 502 is otherwise formed on the high resistivity substrate 402 in a conventional manner in a pattern defined by the mask.

(37) The stepped area adjacent the trap rich region 502 is a “non-TR region” 504. In some embodiments, a filler material 508, such as BOX, may be deposited within the non-TR region 504 adjacent the trap rich region 502 to provide a flatter surface. As should be apparent, more than one trap rich region 502 and more than one non-TR region 504 can be formed in different areas of an SOI wafer 500. When using a filler material 508, essentially all trap rich regions 502 would be surrounded by non-TR regions 504 (some or all of which may be contiguous).

(38) FIG. 5B is a block diagram of an SOI wafer 520 processed in accordance with the teachings of FIG. 5A (the vertical scale has been compressed compared to FIG. 4). A BOX insulator layer 406 has been formed over the trap rich region 502 and the non-TR region 504 (including over the filler material 508, if present) in a conventional manner, and an active layer 408 is then formed over the BOX insulator layer 406 in a conventional manner.

(39) A first variant of the illustrated sequence is to form a trap rich layer on the high resistivity substrate 402, then mask and etch the trap rich layer down to the high resistivity substrate 402 to define non-TR regions 504. In some embodiments, a filler material 508, such as BOX, may be deposited within the non-TR regions 504. Thereafter, a BOX insulator layer 406 and an active layer 408 may be formed, resulting in the structure shown in FIG. 5B (if fillers 508 are used).

(40) A second variant of the illustrated sequence is to form a layer of non-trap rich material (e.g., BOX) on the high resistivity substrate 402, then mask and etch the layer to define regions in which trap rich material is to be formed, then form corresponding trap rich regions 502 within the etched regions. Regions not containing trap rich material would be non-TR regions 504. Thereafter, a BOX insulator layer 406 and an active layer 408 may be formed, resulting in the structure shown in FIG. 5B (if fillers 508 are used).

(41) As illustrated, the non-TR region 504 underlies an area of non-RF circuitry 510 that includes one or more FETs that would be most susceptible to accumulated charge resulting from the interaction of an unmodified trap rich layer 404 and transient changes of state of FETs comprising such circuitry. In contrast, the trap rich region 502 underlies an area of RF circuitry 512 that includes one or more FETs (e.g., FETs in an RF signal path) that generally benefit from the characteristics of the trap rich region 502.

(42) A wide-area non-TR region 504 avoids the problems of aligning FETs with individual “wells” of non-TR regions. As should be apparent, the trap rich region 502 retains all of the normal characteristics of a trap rich layer 404, and thus remains available for fabrication of active layer RF circuitry that can benefit from such characteristics.

(43) Modification of Trap Rich Layer Characteristics Before BOX Layer Formation

(44) In a second embodiment, characteristics of a trap rich layer are modified before formation of a BOX insulator layer.

(45) FIG. 6A is a block diagram showing an in-process step in the manufacture of an SOI wafer 600 having a high resistivity substrate 402 and a trap rich layer 404. In this example, the trap rich layer 404 has already been formed on the high resistivity substrate 402 (shown truncated vertically, the actual proportions would more typically resemble FIG. 4).

(46) Before forming a BOX insulator layer 406 over the trap rich layer 404, a modification is made to regions of the trap rich layer 404 that would underlie one or more FETs that otherwise would be adversely affected by accumulated charge resulting from the interaction of the trap rich layer 404 and active layer devices undergoing transient changes of state. More specifically, a surface modification step 602 is applied to implant or diffuse a selected dopant into the material of selected areas of the trap rich layer 404 so as to damage a region 604 of the trap rich layer 404 sufficiently that its ability to trap such accumulated charge is eliminated or mitigated. More specifically, the damaged region 604 is made more conductive than the trap rich layer 404, allowing accumulated charge to more rapidly dissipate.

(47) The modification step 602 may be carried out in a conventional manner, such as by ion implantation or diffusion through a mask defining the areal extent for the damaged region 604. The selected dopant may be an N-type or P-type dopant, such as phosphorus, arsenic (N-type) or boron (P-type).

(48) After the modification step 602, a BOX insulator layer 406 is formed over the trap rich layer 404 in a conventional manner, and an active layer 408 is then formed over the BOX insulator layer 406 in a conventional manner. One or more FETs 410 are then formed within and/or on the active layer 408 over the damaged region 604. The effects of accumulated charge on such FETs 410 that would otherwise result from the interaction of the trap rich layer 404 and transient changes of state of the FETs 410 are eliminated or mitigated by the underlying damaged region 604.

(49) While only a single FET 410 is shown in FIG. 6A, normally the damaged region 604 of the trap rich layer 404 will extend over an area underlying a plurality of FETs 410, such as FET-based analog circuitry not in the RF signal path. A wide-area damaged region 604 thus avoids the problems of aligning FETs with individual “wells” of damaged trap rich layer 404. As should be apparent, areas of the trap rich layer 404 outside of the damaged region 604 retain all of the normal characteristics of the trap rich layer 404, and thus remain available for fabrication of active layer RF circuitry that can benefit from such characteristics.

(50) For example, FIG. 6B is a block diagram of an SOI wafer 620 processed in accordance with the teachings of FIG. 6A (the vertical scale has been compressed). A damaged region 604 within the trap rich layer 404 underlies an area of non-RF circuitry 610 that includes one or more FETs that would be most susceptible to accumulated charge resulting from the interaction of an unmodified trap rich layer 404 and transient changes of state of FETs comprising such circuitry. In contrast, the trap rich layer 404 remains undamaged underneath an area of RF circuitry 612 that includes one or more FETs (e.g., FETs in an RF signal path).

(51) The amount of doping applied to the damaged region 604 within the trap rich layer 404 may be determined by modeling or empirically, taking into account such factors as the thickness of the BOX insulator layer 406, and the power and switching characteristics of and specifications for the non-RF circuitry 610.

(52) Modification of Trap Rich Layer Characteristics after BOX Layer Formation

(53) In a third embodiment, characteristics of a trap rich layer are modified after formation of a BOX insulator layer (and optionally after formation of an active layer).

(54) FIG. 7A is a block diagram showing an in-process step in the manufacture of an SOI wafer 700 having a high resistivity substrate 402, a trap rich layer 404, and a BOX insulator layer 406. In this example, the trap rich layer 404 and the BOX insulator layer 406 have already been formed on the high resistivity substrate 402 (again, shown truncated vertically, the actual proportions would more typically resemble FIG. 4).

(55) After forming the BOX insulator layer 406 over the trap rich layer 404, a modification is made to regions of the trap rich layer 404 that would underlie one or more FETs that otherwise would be adversely affected by accumulated charge resulting from the interaction of the trap rich layer 404 and active layer devices undergoing transient changes of state. More specifically, a surface modification step 702 is applied to implant a selected dopant through the BOX insulator layer 406 and into the material of selected areas of the trap rich layer 404 so as to damage a region 704 of the trap rich layer 404 sufficiently that its ability to trap such accumulated charge is eliminated or mitigated. More specifically, the damaged region 704 is made more conductive than the trap rich layer 404, allowing accumulated charge to more rapidly dissipate.

(56) The modification step 702 may be carried out in a conventional manner, such as by ion implantation through a mask defining the areal extent for the damaged region 704. The selected dopant may be an N-type or P-type dopant, such as phosphorus, arsenic (N-type) or boron (P-type).

(57) After the modification step 702, an active layer 408 is formed over the BOX insulator layer 406 in a conventional manner. One or more FETs 410 are then formed within and/or on the active layer 408 over the damaged region 704. The effects of accumulated charge on such FETs 410 that would otherwise result from the interaction of the trap rich layer 404 and transient changes of state of the FETs 410 are eliminated or mitigated by the underlying damaged region 704.

(58) While only a single FET 410 is shown in FIG. 7A, normally the damaged region 704 of the trap rich layer 404 will extend over an area underlying a plurality of FETs 410, such as FET-based analog circuitry not in the RF signal path. A wide-area damaged region 704 thus avoids the problems of aligning FETs with individual “wells” of damaged trap rich layer 404. As should be apparent, areas of the trap rich layer 404 outside of the damaged region 704 retain all of the normal characteristics of the trap rich layer 404, and thus remain available for fabrication of active layer RF circuitry that can benefit from such characteristics.

(59) For example, FIG. 7B is a block diagram of an SOI wafer 720 processed in accordance with the teachings of FIG. 7A (the vertical scale has been compressed). A damaged region 704 within the trap rich layer 404 underlies an area of non-RF circuitry 710 that includes one or more FETs that would be most susceptible to accumulated charge resulting from the interaction of an unmodified trap rich layer 404 and transient changes of state of FETs comprising such circuitry. In contrast, the trap rich layer 404 remains undamaged underneath an area of RF circuitry 712 that includes one or more FETs (e.g., FETs in an RF signal path).

(60) FIG. 7C is a block diagram showing a variant in-process step in the manufacture of an SOI wafer 740 having a high resistivity substrate 402, a trap rich layer 404, a BOX insulator layer 406, and an active layer 408. In this example, the trap rich layer 404, the BOX insulator layer 406, and the active layer 408 have already been formed on the high resistivity substrate 402 (again, shown truncated vertically, the actual proportions would more typically resemble FIG. 4).

(61) Again, a modification is made to regions of the trap rich layer 404 that would underlie one or more FETs that otherwise would be adversely affected by accumulated charge resulting from the interaction of the trap rich layer 404 and active layer devices undergoing transient changes of state. More specifically, a surface modification step 702 is applied to implant a selected dopant through the active layer 408 and the BOX insulator layer 406 into the material of selected areas of the trap rich layer 404 so as to damage a region 704 of the trap rich layer 404 sufficiently that its ability to trap such accumulated charge is eliminated or mitigated. More specifically, the damaged region 704 is made more conductive than the trap rich layer 404, allowing accumulated charge to more rapidly dissipate. Processing may continue as shown in FIG. 7B, with formation of non-RF circuitry 710 over the damaged region 704 and formation of RF circuitry 712 over the trap rich layer 404.

(62) As in the embodiment shown by way of example in FIGS. 5A and 5B, the amount of doping applied to the damaged region 704 within the trap rich layer 404 may be determined by modeling or empirically, taking into account such factors as the thickness of the BOX insulator layer 406, and the power and switching characteristics of and specifications for the non-RF circuitry 710.

(63) Laser Modification of Trap Rich Layer Characteristics after BOX Layer Formation

(64) In a fourth embodiment, characteristics of a trap rich layer are modified after formation of a BOX insulator layer (and optionally after formation of an active layer) by using a laser annealing process.

(65) FIG. 8A is a block diagram showing an in-process step in the manufacture of an SOI wafer 800 having a high resistivity substrate 402, a trap rich layer 404, and a BOX insulator layer 406. In this example, the trap rich layer 404 and the BOX insulator layer 406 have already been formed on the high resistivity substrate 402 (again, shown truncated vertically, the actual proportions would more typically resemble FIG. 4). Of note, the BOX insulator layer 406 is essentially transparent to a range of light wavelengths, including infrared.

(66) After forming the BOX insulator layer 406 over the trap rich layer 404, a modification is made to regions of the trap rich layer 404 that would underlie one or more FETs that otherwise would be adversely affected by accumulated charge resulting from the interaction of the trap rich layer 404 and active layer devices undergoing transient changes of state. More specifically, light energy 802 from a focused laser (not shown) is used to anneal the material of selected areas of the trap rich layer 404 so as to change the electrical characteristics of an annealed region 804 of the trap rich layer 404 sufficiently that its ability to trap such accumulated charge is eliminated or mitigated.

(67) In greater detail, a laser is selected having a wavelength that will transmit through the BOX insulator layer 406. Light energy 802 from the laser is focused through the BOX insulator layer 406 onto the trap rich layer 404 to locally melt the trap rich layer 404. As noted above, the trap rich layer 404 is typically formed as a layer of amorphous or polycrystalline silicon on the high resistivity substrate 402, and significantly degrades the mobility of the charge carriers in the thin surface region of the high resistivity substrate 402. However, the amorphous or polycrystalline silicon is not very conductive to current flow. Laser annealing melts the amorphous or polycrystalline silicon and allows recrystallization into larger crystals (or even into a single crystal) that have a higher conductivity to current flow. Accordingly, the annealed region 804 of the trap rich layer 404 is more conductive than the unmodified trap rich layer 404, thus allowing accumulated charge to more rapidly dissipate. Accordingly, the process is similar in a number of ways to the process shown in FIGS. 7A and 7B.

(68) After the laser annealing modification step, an active layer 408 is formed over the BOX insulator layer 406 in a conventional manner. One or more FETs 410 are then formed within and/or on the active layer 408 over the annealed region 804. The effects of accumulated charge on such FETs 410 that would otherwise result from the interaction of the trap rich layer 404 and transient changes of state of the FETs 410 are eliminated or mitigated by the underlying annealed region 804.

(69) While only a single FET 410 is shown in FIG. 8A, normally the annealed region 804 of the trap rich layer 404 will extend over an area underlying a plurality of FETs 410, such as FET-based analog circuitry not in the RF signal path. A wide-area annealed region 804 thus avoids the problems of aligning FETs with individual “wells” of annealed trap rich layer 404. As should be apparent, areas of the trap rich layer 404 outside of the annealed region 804 retain all of the normal characteristics of the trap rich layer 404, and thus remain available for fabrication of active layer RF circuitry that can benefit from such characteristics.

(70) For example, FIG. 8B is a block diagram of an SOI wafer 820 processed in accordance with the teachings of FIG. 8A (the vertical scale has been compressed). An annealed region 804 within the trap rich layer 404 underlies an area of non-RF circuitry 810 that includes one or more FETs that would be most susceptible to accumulated charge resulting from the interaction of an unmodified trap rich layer 404 and transient changes of state of FETs comprising such circuitry. In contrast, the trap rich layer 404 remains unchanged underneath an area of RF circuitry 812 that includes one or more FETs (e.g., FETs in an RF signal path).

(71) FIG. 8C is a block diagram showing a variant in-process step in the manufacture of an SOI wafer 840 having a high resistivity substrate 402, a trap rich layer 404, a BOX insulator layer 406, and an active layer 408. In this example, the trap rich layer 404, the BOX insulator layer 406, and the active layer 408 have already been formed on the high resistivity substrate 402 (again, shown truncated vertically, the actual proportions would more typically resemble FIG. 4). As with FIG. 8A, the BOX insulator layer 406 is essentially transparent to a range of light wavelengths, including infrared.

(72) A modification is made to regions of the trap rich layer 404 that would underlie one or more FETs that otherwise would be adversely affected by accumulated charge resulting from the interaction of the trap rich layer 404 and active layer devices undergoing transient changes of state. More specifically, light energy 802 from a focused laser (not shown) is used to anneal the material of selected areas of the trap rich layer 404 so as to change the electrical characteristics of an annealed region 804 of the trap rich layer 404 sufficiently that its ability to trap such accumulated charge is eliminated or mitigated. As described with respect to FIG. 8A, the laser is selected to have a wavelength that will transmit through the BOX insulator layer 406. Light energy 802 from the laser is focused through the active layer 408 and the BOX insulator layer 406 onto the trap rich layer 404 to locally melt the trap rich layer 404 to form the annealed region 804. The active layer 408 is very thin and will absorb little energy from the laser beam. As with the embodiment of FIG. 8A, the annealed region 804 of the trap rich layer 404 is more conductive than the unmodified trap rich layer 404, thus allowing accumulated charge to more rapidly dissipate. Processing may continue as shown in FIG. 8B, with formation of non-RF circuitry 810 over the annealed region 804 and formation of RF circuitry 812 over the trap rich layer 404. In some embodiments, laser annealing may be performed after formation of non-RF circuitry 810 over a region, thereby converting that region to an annealed region 804.

(73) Modification of Trap Rich Layer after Wafer Fabrication

(74) In a fifth embodiment, a trap rich layer of a pre-fabricated SOI wafer is modified by removal of selected regions of the trap rich layer.

(75) FIG. 9A is a block diagram of a fabricated SOI wafer 900. As illustrated, the SOI wafer 900 includes a silicon high resistivity substrate 402, a trap rich layer 404, a BOX insulator layer 406, and an active layer 408. As noted above, pre-fabricated SOI wafers having the illustrated configuration are commercially available.

(76) FIG. 9B is a block diagram of an etched fabricated SOI wafer 920. In this example, a mask has been applied and the SOI wafer 920 has been etched in a conventional manner to create a void 902 down through the BOX insulator layer 406 and the trap rich layer 404 to the high resistivity substrate 402.

(77) FIG. 9C is a block diagram of an etched SOI wafer 940 processed in accordance with the teachings of FIG. 9B. Non-RF circuitry 910 may be formed in a conventional manner directly on the high resistivity substrate 402, rather than over the trap rich layer 404. The non-RF circuitry 910 may generally include one or more FETs that would be most susceptible to accumulated charge resulting from the interaction of an unmodified trap rich layer 404 and transient changes of state of FETs comprising such circuitry. As illustrated, an area of RF circuitry 912 that includes one or more FETs that generally benefit from the characteristics of a trap rich layer (e.g., FETs in an RF signal path) may be formed over the remaining trap rich layer 404.

(78) FIG. 9D is a block diagram of a variant of an etched SOI wafer 960 processed in accordance with the teachings of FIG. 9B. A silicon epitaxial layer 914 is be formed over the bare high resistivity substrate 402 of FIG. 9B using conventional masking and epitaxial growth techniques. In the illustrated example, the epitaxial layer 914 is shown as completely filling the void 902 of FIG. 9B. However, the epitaxial layer 914 may be grown to a level that does not completely fill the void 902, or which over-fills the void 902. Non-RF circuitry 910 may then be formed on the epitaxial layer 914 in a conventional manner.

(79) Modification of Trap Rich Wafer after Wafer Fabrication

(80) In a sixth embodiment, a pre-fabricated SOI wafer having a trap rich layer is modified by building up a raised region.

(81) FIG. 10A is a block diagram of a fabricated SOI wafer 1000. As illustrated, the SOI wafer 1000 includes a silicon high resistivity substrate 402, a trap rich layer 404, a BOX insulator layer 406, and an active layer 408. As noted above, pre-fabricated SOI wafers having the illustrated configuration are commercially available.

(82) FIG. 10B is a block diagram of an augmented SOI wafer 1020. In this example, a mask has been applied and a raised region 1002 of silicon has been formed in a conventional manner to create a raised region above the active layer 408.

(83) FIG. 10C is a block diagram of an augmented SOI wafer 1040 processed in accordance with the teachings of FIG. 10B. Non-RF circuitry 1010 may be formed in a conventional manner on the raised region 1002, spaced further from the trap rich layer 404 than if formed directly on the active layer 408. The increased spacing will make the raised region 1002 behave more like a bulk substrate with respect to FETs fabricated on the raised region 1002, thereby reducing the formation and influence of accumulated charge near the trap rich layer 404.

(84) The non-RF circuitry 1010 may generally include one or more FETs that would be most susceptible to accumulated charge resulting from the interaction of an unmodified trap rich layer 404 and transient changes of state of FETs comprising such circuitry. As illustrated, an area of RF circuitry 1012 that includes one or more FETs that generally benefit from the characteristics of a trap rich layer (e.g., FETs in an RF signal path) may be formed over the trap rich layer 404 elsewhere on the SOI wafer 1040.

(85) Substrate Stabilization

(86) Additional techniques may optionally be used in conjunction with embodiments described above. For example, in some embodiments, it may be useful to create protected areas on an SOI substrate that encompass FETs that are sensitive to accumulated charge effects by surrounding such areas with substrate contacts (S-contacts), such as the type of S-contacts taught in U.S. patent application Ser. No. 14/964,412 referenced above.

(87) An S-contact in the context of an IC structure is a path which provides a resistive conduction path between a contact region at a surface of a layer of the IC structure and a contact region at or near a surface of a high resistivity substrate of the IC structure (high resistivity includes a range of 3,000 to 20,000 or higher ohm-cm; as known to a person skilled in the art, standard SOI process uses substrates with a low resistivity, typically below 1,000 ohm-cm).

(88) For example, FIG. 11 is block diagram showing an SOI IC structure 1100 with a trap rich layer 404, a BOX insulator layer 406, and substrate contacts for a single FET 410. In the illustrated embodiment, which is otherwise similar to FIG. 4, two S-contacts 1102a, 1102b penetrate through corresponding isolation regions 1104 from the active layer 408 to or near the upper surface of the high resistivity substrate 402. The material used for the S-contacts 1102a, 1102b can be any low resistivity conductive material, such as polysilicon and various metals (e.g., tungsten, copper, etc.). In the case of an SOI device, the isolation regions 1104 can be shallow trench isolation (STI) regions. By virtue of penetrating through the isolation regions 1104 within the active layer 408, the S-contacts remain isolated from direct contact with other active regions of the active layer 408. In common practice, the S-contacts 1102a, 1102b are electrically connected, directly or through other circuit elements, to the source S or the gate G of a FET 410; one possible electrical connection is shown by a dotted line 1106 from the source S of the FET 410 to one S-contact 1102a (other possible contacts are not shown here, but are illustrated in U.S. patent application Ser. No. 14/964,412 referenced above). However, as discussed below, the S-contacts 1102a, 1102b may electrically connected to circuit ground or to another known potential.

(89) In the case of SOI substrates having a trap rich layer 404, as shown in FIG. 11, an S-contact 1102a can penetrate through the trap rich layer 404 to make direct contact with the high resistivity substrate 402. Alternatively, since the trap rich layer 404 has some conductivity (and may be as conductive as the high resistivity substrate 402), in some applications an S-contact 1102b can make a resistive contact with the high resistivity substrate 402 by contacting the surface of the trap rich layer 404. In other applications, an S-contact 1102b can penetrate the trap rich layer 404 to a depth sufficient enough to make a resistive contact, through a remaining portion of the thickness of the trap rich layer 404, with the high resistivity substrate 402.

(90) In addition to the purposes taught in U.S. patent application Ser. No. 14/964,412 referenced above, S-contacts can be used in conjunction with embodiments of the invention (such as the embodiments described above) to create protected areas on an IC substrate that encompass FETs that are sensitive to accumulated charge effects. For example, FIG. 12 is a top plan view of an area 1200 of a stylized IC that includes twelve example circuits 1202 of a type susceptible to accumulated charge resulting from the interaction of an unmodified trap rich layer 404 and transient changes of state of FETs comprising such circuits (e.g., current mirrors for bias circuits of a power amplifier). FIG. 13 is a top plan view of an area 1300 of a stylized IC that includes the twelve example circuits 1202 of FIG. 12 surrounded by a plurality of S-contacts 1302. As illustrated, S-contacts 1302 substantially surround each circuit 1202, essentially creating corresponding “wells” surrounded by S-contact “rings” (even though not circular). The rings of S-contacts 1302 around the wells reduce substrate impedance and thus settling time of the substrate voltage under the circuits 1202, help in shielding the circuits 1202 from electrical interference (from each other and from other circuits outside the area 1300), help in draining accumulated charge from the high resistivity substrate 402 and/or trap rich layer 404, and help to improve impedance matching for the circuits 1202 within the wells by preventing uneven substrate potential between circuits. However, even a single S-contact near a circuit 1202 may provide a benefit.

(91) Each of the S-contacts 1302 may be electrically connected, directly or through other circuit elements, to the source S or the gate G of a FET. However, when used with embodiments of the present invention, it may be quite beneficial to connect the S-contacts 1302 to circuit ground or to another known potential (even the IC supply voltage, V.sub.DD), to avoid imposing signals on the S-contacts 1302. Such imposed signals may create accumulated charge in the high resistivity substrate 402 and/or in or near the trap layer 404 and/or elsewhere in the FET (e.g., at the gate, drain, or source of the FET), and may arise, e.g., due to varying voltages applied to active layer 408 elements, such as the source S or gate G of a FET. While a static potential may be most beneficial in some applications, in other applications it may be useful to dynamically change the potential applied to the S-contacts 1302, such as by raising or lowering an applied voltage to counteract accumulated charge that arises during some operational phases (e.g., bursts of signal transmissions in an active mode versus essentially quiescent periods during a standby mode). In some applications, it may be useful to purposefully inject charge into the high resistivity substrate 402 and/or the trap layer 404 by biasing the S-contacts 1302 with a suitable voltage signal. When a potential other than circuit ground is desired, it may be useful use a charge pump or similar means to inject offsetting charge, or apply a negative potential, or apply a positive potential that exceeds the voltage of the IC power supply (e.g., greater than V.sub.DD).

(92) The size, number, and spacing of the S-contacts 1302 generally is a matter of design choice. However, to improve transient effects, wells defined by the S-contacts 1302 should be small enough such that there are essentially no gradients under large circuits 1202 that might necessitate additional impedance matching. Accordingly, the size of the S-contact rings should be similar in size to the wells of potential formed by the S-contacts. Note that complete encirclement of each circuit 1202 may not be necessary in all applications, and that a partial ring of S-contacts may suffice. For example, S-contacts may be omitted in some applications for edges of circuits 1202 not shared with other close-by circuits 1202, such as the S-contacts shown within the dotted oval 1306 of FIG. 13. Moreover, while individual “island” type S-contacts 1302 are illustrated in FIG. 13, S-contacts can be formed as trenches, in known fashion.

(93) If the S-contacts 1302 are biased in some manner, it may be useful to form a guard ring 1308 of S-contacts around the area 1300 to protect other circuitry; S-contact trenches would work particularly well for such a guard ring 1308, which typically would be grounded.

(94) In addition to the methods taught in U.S. patent application Ser. No. 14/964,412 referenced above, a person skilled in the art will know of many fabrication methods to provide S-contacts suitable for the purposes described in this disclosure.

(95) As an example of combining the above-disclosed concepts, FIG. 14 is block diagram showing an SOI IC structure 1400 with a trap rich layer 404, a BOX insulator layer 406, and substrate contacts for a single FET 410. In the illustrated embodiment, which is otherwise similar to FIG. 11, two S-contacts 1402a, 1402b penetrate through corresponding isolation regions 1104 from the active layer 408 to a modified region 1404 of the trap rich layer 404.

(96) The modified region 1402 may be the result of any of: modification of the trap rich layer 404 characteristics before formation of the BOX insulator layer 406, as described above with respect to FIGS. 6A-6B; modification of the trap rich layer 404 characteristics after formation of the BOX insulator layer 406, as described above with respect to FIGS. 7A-7C; or laser annealing of the trap rich layer 404, as described above with respect to FIGS. 8A-8C. One or more S-contacts may also be used in conjunction with the embodiments shown in FIGS. 5A-5B, 9A-9D, 10A-10C by contacting the high resistivity substrate 402 and/or a trap rich layer 404 or region 502.

(97) By virtue of penetrating through the isolation regions 1104 within the active layer 408, the S-contacts 1402a, 1402b remain isolated from direct contact with other active regions of the active layer 408. The S-contacts 1402a, 1402b may electrically connected, directly or through other circuit elements, to circuit ground or to another known static or dynamic potential, as described above. Modification of the modified region 1402 makes that region more conductive than the trap rich layer 404, allowing accumulated charge to more rapidly dissipate. Since the S-contacts 1402a, 1402b are in electrical contact with the modified region 1402, they can conduct such accumulated charge to a known potential.

(98) Methods

(99) Another aspect of the invention includes methods for forming a silicon-on-insulator (SOI) integrated circuit. Following are examples of such methods:

(100) FIG. 15 is a process flow diagram 1500 showing a first method for forming a silicon-on-insulator (SOI) integrated circuit on a substrate, including: forming a layer of at least one trap rich region and at least one non-trap rich region on the substrate (STEP 1502); forming an insulator layer on the layer of at least one trap rich region and at least one non-trap rich region (STEP 1504); forming an active layer on the insulator layer (STEP 1506); and fabricating circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry in and/or on the active layer above at least one non-trap rich region (STEP 1508).

(101) FIG. 16 is a process flow diagram 1600 showing a second method for forming a silicon-on-insulator (SOI) integrated circuit on a substrate, including: forming a trap rich layer on the substrate (STEP 1602); forming at least one modified region within the trap rich layer that is more conductive than the trap rich layer (STEP 1604); forming an insulator layer on the trap rich layer (STEP 1606); forming an active layer on the insulator layer (STEP 1608); and fabricating circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry in and/or on the active layer above at least one of the modified regions (STEP 1610).

(102) FIG. 17 is a process flow diagram 1700 showing a third method for forming a silicon-on-insulator (SOI) integrated circuit on a substrate, including: forming a trap rich layer on the substrate (STEP 1702); forming an insulator layer on the trap rich layer (STEP 1704); forming an active layer on the insulator layer (STEP 1706); forming a void through the active layer, the underlying insulator layer, and the underlying trap rich layer to the substrate to define at least one non-trap rich region (STEP 1708); and fabricating circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry in at least one of the non-trap rich regions (STEP 1710).

(103) FIG. 18 is a process flow diagram 1800 showing a fourth method for forming a silicon-on-insulator (SOI) integrated circuit on a substrate, including: forming a trap rich layer on the substrate (STEP 1802); forming an insulator layer on the trap rich layer (STEP 1804); forming an active layer on the insulator layer (STEP 1806); forming a raised region on the active layer (STEP 1808); and fabricating circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry in at least one of the raised regions (STEP 1810).

(104) Other aspects of the above methods may include one or more of the following: fabricating circuitry that can benefit from the characteristics of the trap rich region in and/or on the active layer above at least one trap rich region or layer; forming the layer of at least one trap rich region and at least one non-trap rich region by forming a layer of non-trap rich material on the high resistivity substrate, masking and etching through the layer of non-trap rich material to the high resistivity substrate to define at least one region in which trap rich material is to be formed; and forming trap rich material within at least one such region to define the at least one trap rich region; forming the layer of at least one trap rich region and at least one non-trap rich region by forming a layer of trap rich material on the high resistivity substrate, and masking and etching the trap rich material through to the high resistivity substrate to define the at least one non-trap rich region; forming the layer of at least one trap rich region and at least one non-trap rich region by masking the high resistivity substrate to define at least one region in which trap rich material is to be formed, and forming trap rich material within at least one such region to define the at least one trap rich region; forming a filler material within each non-trap rich region before forming the insulator layer on the layer of at least one trap rich region and at least one non-trap rich region; each modified region being formed by implanting or diffusing a dopant into a selected area of the trap rich layer before forming the insulator layer on the trap rich layer; each modified region being formed by implanting a dopant into a selected area of the trap rich layer after forming the insulator layer on the trap rich layer; each modified region being formed by laser annealing a selected area of the trap rich layer after forming the insulator layer on the trap rich layer; forming an epitaxial material on the high resistivity substrate within each void, and fabricating the circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry on the epitaxial material; forming one or more (e.g., at least a partial ring) substrate contacts (S-contacts) near or around at least one area of circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry and/or the substrate being a high resistivity substrate.

(105) Options and Fabrication Technologies

(106) As one of ordinary skill in the art will appreciate, additional layers and steps may be added to any of the structures shown in FIGS. 5A-18 without deviating from the inventive concepts. Similarly, the order of layer formation may vary without deviating from the inventive concepts. For example, using known layer transfer technologies, a BOX insulator layer 406 and an active layer 408 may be formed on a handle substrate and bonded as a unit to a trap rich layer 404 formed on a high resistivity substrate 402. Such a process is well suited to the practice of the embodiment described above with respect to FIGS. 5A-5B and 6A-6B, since the trap rich layer 502, 404 is easily accessible for processing. Note also that the term “forming” with respect to forming a BOX insulator layer 406 on a trap rich layer 404 or region 502 (or the like) includes any known method, including deposition of material to create the BOX insulator layer 406 and bonding a pre-fabricated BOX insulator layer 406 on a trap rich layer 404 or region 502.

(107) While normally a trap rich layer 404 or region 502 is used in conjunction with a high resistivity substrate 402, the invention has applicability to bulk (low resistivity) substrates on which a trap rich layer 404 or region 502 has been formed (e.g., by a damaging implant). Further, while it is beneficial in general to fabricate FETs that would be susceptible to trap rich related accumulated charge over a non-TR region or layer, such FETs may also be fabricated over a trap rich region or layer in some applications. For example, FET-based circuitry fabricated over a trap rich region or layer may utilize a circuit that compensates for or mitigates the problems of trap rich related accumulated charge, such as the circuits taught in U.S. patent application Ser. No. 15/600,579 filed May 19, 2017, entitled “Transient Stabilized SOI FETs”, referenced above. Moreover, in some applications, some RF circuitry may be fabricated over a non-TR region or layer if such circuity is not overly sensitive to linearity degradation (linearity is benefited by the characteristics of a trap rich region or layer).

(108) A number of the inventive methods described above can be practiced on commercial SOI wafers that come pre-fabricated with a high resistivity substrate 402, a trap rich layer 404, a BOX insulator layer 406, and an active layer 408. Such pre-fabricated wafers are well suited to the practice of the embodiments described above with respect to FIGS. 7B-7C, 8B-8C, 9A-9D, and 10A-10D.

(109) The term “MOSFET”, as used in this disclosure, means any field effect transistor (FET) with an insulated gate and comprising a metal or metal-like, insulator, and semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

(110) As should be readily apparent to one of ordinary skill in the art, various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable IC technology (including but not limited to MOSFET and IGFET structures) that exhibits accumulated charge, including (but not limited to) silicon-on-insulator (SOI).

(111) Voltage levels may be adjusted or voltage and/or logic signal polarities reversed depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functional without significantly altering the functionality of the disclosed circuits.

(112) The term “circuit ground” includes a reference potential, and is not limited to an earth ground or other “hard” ground.

(113) A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion.

(114) It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).