Thermal interface material having defined thermal, mechanical and electric properties

Abstract

An electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating part of the carrier and the electronic chip, and an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant, wherein the interface structure has a compressibility in a range between 1% and 20%, in particular in a range between 5% and 15%.

Claims

1. An electronic component, the electronic component comprising: an electrically conductive carrier; an electronic chip on the carrier; an encapsulant encapsulating part of the carrier and the electronic chip; an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant; wherein the interface structure has a compressibility in a range between 1% and 20%, in particular in a range between 5% and 15%.

2. The electronic component according to claim 1, wherein the interface structure has a Vickers hardness in a range between 0.50 N/mm.sup.2 and 3 N/mm.sup.2, in particular in a range between 0.85 N/mm.sup.2 and 1.50 N/mm.sup.2, at a measuring force of 1 N.

3. The electronic component according to claim 1, wherein the interface structure has a Young modulus in a range between 0.1 GPa and 2 GPa, in particular in a range between 0.3 GPa and 1.5 GPa.

4. The electronic component according to claim 1, comprising at least one of the following features: the interface structure shows a scratch resistance at a measuring force of 1 N without effect on an electrical breakdown voltage of at least 5.6 kV; the interface structure shows a scratch resistance at a measuring force of 1 N without effect on an electrical breakdown voltage per thickness of at least 10 kV/mm.

5. The electronic component according to claim 1, wherein the interface structure has a thickness in a range between 50 m and 600 m, in particular in a range 100 m and 400 m.

6. The electronic component according to claim 1, comprising at least one of the following features: the interface structure has an electric breakdown voltage of at least 2 kV, in particular of at least 5 kV, more particularly in a range between 5 kV and 12 kV; the interface structure has an electric breakdown voltage per thickness of at least 5 kV/mm, in particular of at least 10 kV/mm, more particularly of at least 15 kV/mm.

7. The electronic component according to claim 1, wherein the interface structure has a thermal conductivity of at least 1 W m.sup.1 K.sup.1, in particular of at least 2 W m.sup.1 K.sup.1, more particularly in a range between 3 W m.sup.1 K.sup.1 and 20 W m.sup.1 K.sup.1.

8. The electronic component according to claim 1, wherein the interface structure comprises or consists of a soft polymer matrix filled with filler particles.

9. The electronic component according to claim 1, wherein the interface structure in combination with the carrier and a heat dissipation body to be attached to an external surface of the interface structure has a capacitance in a range between 10 pF and 100 pF, in particular in a range between 25 pF and 55 pF.

10. The electronic component according to claim 1, wherein the interface structure, the covered exposed surface portion of the carrier and the connected surface portion of the encapsulant are integrally formed with one another, in particular so that the interface structure is not detachable from a remainder of the electronic component.

11. The electronic component according to claim 1, wherein material of the interface structure is intermingled with material of the covered exposed surface portion of the carrier and material of the connected surface portion of the encapsulant.

12. The electronic component according to claim 1, wherein the interface structure extends over an entire bottom surface of the encapsulant and over the entire exposed surface portion of the carrier at a bottom of the electronic component.

13. The electronic component according to claim 1, wherein the interface structure has a relative permittivity in a range between 1.5 and 6, in particular in a range between 4 and 5.

14. The electronic component according to claim 1, wherein the carrier comprises a plurality of galvanically insulated separate carrier regions.

15. The electronic component according to claim 1, wherein the carrier comprises a plurality of sections of different thicknesses.

16. The electronic component according to claim 1, wherein the electrically insulating and thermally conductive interface structure is configured to be attached at an external surface to a heat dissipation body.

17. An arrangement, the arrangement comprising: a mounting structure comprising an electric contact; an electronic component according to claim 1 mounted on the mounting structure so that the electronic chip is electrically connected to the electric contact.

18. An electrically insulating and thermally conductive interface material for integration with an electronic component, wherein the interface material has a compressibility in a range between 1% and 20%, in particular in a range between 5% and 15%.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0080] The accompanying drawings, which are included to provide a further understanding of exemplary embodiments and constitute a part of the specification, illustrate exemplary embodiments.

[0081] In the drawings:

[0082] FIG. 1 illustrates a cross-sectional view of an electronic component according to an exemplary embodiment of the invention, to be mounted on a mounting structure for establishing an arrangement according to an exemplary embodiment of the invention.

[0083] FIG. 2 illustrates a diagram illustrating a dependence of Vickers hardness from a product of thermal conductivity and breakdown voltage per thickness of a material of an interface structure of an electronic component according to an exemplary embodiment of the invention.

[0084] FIG. 3 illustrates an SEM image of aluminum oxide filled silicone as material for an interface structure of an electronic component having a conductive carrier according to an exemplary embodiment of the invention.

[0085] FIG. 4 illustrates different views of electronic components according to exemplary embodiments of the invention.

[0086] FIG. 5 illustrates a plan view of an electronic component according to an exemplary embodiment of the invention having multiple galvanically insulated separate carrier regions.

[0087] FIG. 6 illustrates a plan view of an electronic component according to another exemplary embodiment of the invention having multiple galvanically insulated separate carrier regions.

[0088] FIG. 7 illustrates a plan view of an electronic component according to yet another exemplary embodiment of the invention having multiple separate carrier regions.

[0089] FIG. 8 illustrates a circuit diagram illustrating the electronic functionality of the electronic component according to FIG. 7.

[0090] FIG. 9 illustrates a cross-sectional view of an electronic component according to an exemplary embodiment of the invention having a carrier with multiple different sections of different thickness.

[0091] FIG. 10 illustrates a cross-sectional view of an electronic component according to an exemplary embodiment of the invention having multiple galvanically insulated separate carrier regions connected to one another by a bond wire.

DETAILED DESCRIPTION

[0092] The illustration in the drawing is schematically and not to scale.

[0093] Before exemplary embodiments will be described in more detail referring to the figures, some general considerations will be summarized based on which exemplary embodiments have been developed.

[0094] An exemplary embodiment provides an electronic component or package configured as a discrete device with specifically adapted thermal interface contact(s). More specifically, a coating material may be placed as thermal interface structure on an exposed metal (in particular copper) surface of the package (in particular a TO-package) with a defined softness of the layer. Thus, it is possible to assemble the thermal interface structure as a one-layer substrate having a high electrical isolation and at the same time low stiffness for efficiently promoting surface wetting of a mounted heat dissipation body such as a cooling unit. The electrical, thermal and mechanical properties (for instance stiffness) of the thermal interface structure can be specifically matched so as to obtain one, some or all of the following technical advantages: [0095] A reduced effort for providing the thermal interface material may be achieved, and easier processing at customer location may be enabled. By attaching a TIM layer to the package, the package can be used in a plug and play mode, without the need to apply an additional isolation or contact medium. In this context, a sufficient softness of the TIM is advantageous, as well as a sufficient compressibility in order to balance out an uneven surface. [0096] An improved reliability may be obtained, since no local movement of paste materials at mounted status especially at operation cycles occurs. A constant pressure (i.e. pressing-on-the-workpiece pressure exerted during mounting, for instance during screwing or clipping, the package or electronic component onto the heat dissipation body) and a constant layer thickness are possible. [0097] An improvement of the thermal performance is possible with a molded thermal interface material according to an exemplary embodiment of the invention compared to thermal grease and also compared to conventional thermal interface foils due to the reduced thermal contact resistance between the interface material and the chip carrier, in particular when specially filled polymers are used. [0098] A manufacturer may deliver the total electronic component as a system solution without any danger that performance of the electronic component may be decreased by the use of low-grade grease or the like by an end user. [0099] Especially for applications like solar cells, inductive heating, inductive welding, UPS, etc. with continuous operation and reduced leadframe thickness (single gauge), a package with thermal interface material according to an exemplary embodiment of the invention may be used in a cost efficient and reliable way. [0100] Certain application designs, so-called single end topologies, may benefit from a decoupling of the package backside (drain) from the cooling unit (for instance a heat sink made of aluminum). This may reduce noise levels for the complete electronic circuits (close to the heat sink). Disturbances originating from rapid voltage jumps at the heat sink can lead to higher EMR (electromagnetic radiation), for instance trigger undesired gate-on signals (which may result in an undesired destruction of the gate driver).

[0101] Exemplary embodiments of the invention may enable the delivery of TO-packages without the need of conventional TIM or grease for mounting the package on a cooling unit by an assembly of the thermal interface layer on the package at the copper surface of the carrier. Such a thermal interface layer or layer system according to an exemplary embodiment of the invention may combine at least part of the following properties: [0102] Thickness: between 70 m and 300 m (for example 250 m) [0103] Polymer matrix: silicone [0104] Type of filler of thermal interface layer: Al.sub.2O.sub.3, SiO.sub.2, BN, AlN with a filling degree of between 90 mass % and 95 mass % [0105] Thermal conductivity: 2 W/mK to 15 W/mK (which may for instance be measured by laser flash analysis) [0106] Electrical isolation capability: for a thickness of 200 m, the electrical breakdown AC peak voltage may be at least 2.5 kV (for instance at a thickness of 250 m), in particular at least 8 kV. By varying the thickness of the thermal interface layer and the content of filler particles as design parameters, it is possible to cover at least a range between 5.6 kV and 12 kV. [0107] Vickers hardness (HV) may be at or below 3 N/mm.sup.2, preferably within a range of 20% around 1 N/mm.sup.2. This corresponds to a value of the Young modulus of 20% around 0.6 GPa. [0108] With the characterized material, scratch resistance may be achieved at 1 N force without effect on electrical breakdown specification of 5.6 kV (AC peak). [0109] The dielectrical constant .sub.r may range from 3 to 5. The capacitance value of the dielectric thermal interface structure sandwiched between two electrically conductive structures (carrier, heat dissipation body) may be in a range between 25 pF and 55 pF. [0110] Compressibility of the thermal interface material may be between 1% to 20% (at maximal force of 18 N). [0111] Package types which may be preferably equipped with the described thermal interface material are Transistor Outline (TO) packages, intelligent power modules (IPM), and all other modules with one or more packaged semiconductor chips. [0112] The thermal interface material may have a comparative tracking index of 600 or more. [0113] Creeping at a force of 1 N may be in a range of 15% around 5.6%.

[0114] The thermal interface material may be provided on the package as a single layer (for instance by using an Al.sub.2O.sub.3 filled silicone with a specially adapted stiffness. Fine tuning of the desired material properties in terms of a specific application can be performed for instance by a special filler size distribution in combination with a special crosslinking density of the matrix polymer. As one important criterion for advantageous mechanical properties, a layer compressibility between 1% and 20% at ordinary mounting torque ratios (i.e. when connecting the package with a heat dissipation body by screwing a screw through the package and into the heat dissipation body) can be determined. Configuring the thermal interface structure as a single layer renders an additional adhesion layer or the like dispensable, since the intrinsic properties of the thermal interface structure may provide for an adhesion function as well.

[0115] According to a preferred embodiment of the invention, a thermal interface structure embodied as coating material may be placed on a copper surface of a chip carrier of the electronic component (such as a TO-package) with a defined softness of the coating layer. The mechanical properties (for instance stiffness) of the thermal interface layer can be described by: [0116] Vickers hardness at or below 3 N/mm.sup.2, in particular in a range of 15% around HV 1 N/mm.sup.2 (HM 10 N/mm.sup.2) at 1N measuring force. [0117] Indention depth at 1N force of Vickers indentor not more than 50 m, in particular not more than 30 m (for instance at a total thickness of the thermal interface layer of at least 200 m). [0118] Young modulus in a range of 15% around 0.6 GPa [0119] Creeping at 1N force in a range of 15% around 5.6% [0120] Scratch resistance at 1N force without effect on electrical breakdown specification of 5.6 kV (AC peak) [0121] Compressibility of layer in a range between 1% and 20%, preferably 10% (at a maximum force of 18 N, 0.1 MPa).

[0122] However, it has been determined by the present inventors that a decisive criterion as to whether a material is particularly appropriate as thermal interface structure for a package or an electronic component can be formulated as a combination of a high breakdown voltage per thickness of the interface material [kV/mm] with a high thermal conductivity [W/mK] of the thermal interface layer including a pronounced softness (indicated by the square of the Vickers hardness [N.sup.2/mm.sup.4]). These requirements may be specified by a physical unit, which may be denoted as MAME, and which should have a value of at least 1 kV W mm.sup.3 m.sup.1 K.sup.1 N.sup.2.

[0123] Corresponding definitions are:

[0124] Vbr=Breakthrough Voltage per thickness [kV/mm]

[0125] =Thermal conductivity [W/(mK)]

[0126] HV=Vickers hardness at 1N force [N/mm.sup.2]

[0127] MAME=(Vbr*)/HV.sup.2 [1 kV W mm.sup.3 m.sup.1 K.sup.1 N.sup.2]

[0128] It has turned out that when the value MAME is at least kV W mm.sup.3 m.sup.1 K.sup.1 N.sup.2, excellent results in terms of electrical (high breakdown voltage and thus reliable electric isolation), mechanical (sufficient softness to promote low thermal resistivity at interface between thermal interface structure and heat dissipation body) and thermal properties (high intrinsic thermal conductivity) can be achieved. When the value MAME is at least 3 kV W mm.sup.3 m.sup.1 K.sup.1 N.sup.2, outstanding results in terms of electrical, mechanical and thermal properties can be obtained.

[0129] These properties, as indicated by the physical parameter MAME, may be preferably combined with at least one of the following other layer characteristics: [0130] thickness of the thermal interface structure of at least 200 m, for instance 250 m, (to obtain sufficient mechanical stability and scratch resistance) [0131] electrical breakdown voltage of at least 10 kV/mm (AC peak) to ensure electrical stability even for power applications [0132] comparative tracking index of at least 600 [0133] thermal conductivity of at least 2 W/mK (to ensure a sufficient amount of heat removal during operation of the electronic component)

[0134] With such a combination of material parameters, assembly of a one-layer substrate showing a high electrical isolation and at the same time low stiffness for proper surface wetting of the cooling unit is possible.

[0135] Such an embodiment of the invention enables the provision of TO-packages without the need of a conventional TIM or grease for mounting on a cooling unit by an assembly of the described thermal interface layer on the TO-package at the copper surface. Such a thermal interface layer or layer system combines high electrical isolation strength (electrical breakdown voltage above 5 kV) and high thermal conductivity (thermal resistivity below 0.5 K/W) with reliable contact area or wetting to a heat dissipation body such as a cooling unit.

[0136] FIG. 1 illustrates a cross-sectional view of an electronic component 100, which is embodied as a Transistor Outline (TO) package, according to an exemplary embodiment of the invention. The electronic component 100 is mounted on a mounting structure 132, here embodied as printed circuit board, for establishing an arrangement 130 according to an exemplary embodiment of the invention.

[0137] The mounting structure 132 comprises an electric contact 134 embodied as a plating in a through hole of the mounting structure 132. When the electronic component 100 is mounted on the mounting structure 132, an electronic chip 104 of the electronic component 100 is electrically connected to the electric contact 134 via an electrically conductive carrier 102, here embodied as a leadframe made of copper, of the electronic component 100.

[0138] The electronic component 100 comprises the electrically conductive carrier 102, the electronic chip 104 (which is here embodied as a power semiconductor chip) adhesively (see reference numeral 136) mounted on the carrier 102, and an encapsulant 106 (here embodied as mold compound) encapsulating part of the carrier 102 and part of the electronic chip 104. As can be taken from FIG. 1, a pad on an upper main surface of the electronic chip 104 is electrically coupled to the carrier 102 via a bond wire 110.

[0139] During operation of the power package or electronic component 100, the power semiconductor chip in form of the electronic chip 104 generates a considerable amount of heat. At the same time, it must be ensured that any undesired current flow between a bottom surface of the electronic component 100 and an environment is reliably avoided.

[0140] For ensuring electrical insulation of the electronic chip 104 and removing heat from an interior of the electronic chip 104 towards an environment, an electrically insulating and thermally conductive interface structure 108 is provided which covers an exposed surface portion of the carrier 102 and a connected surface portion of the encapsulant 106 at the bottom of the electronic component 100. The electrically insulating property of the interface structure 108 prevents undesired current flow even in the presence of high voltages between an interior and an exterior of the electronic component 100. The thermally conductive property of the interface structure 108 promotes a removal of heat from the electronic chip 104, via the electrically conductive carrier 102 (of thermally properly conductive copper), through the interface structure 108 and towards a heat dissipation body 112. The heat dissipation body 112, which may be made of a highly thermally conductive material such as copper or aluminum, has a base body 114 directly connected to the interface structure 108 and has a plurality of cooling fins 116 extending from the base body 114 and in parallel to one another so as to remove the heat towards the environment. A mechanically soft and compressible property of the interface structure 108 ensures that when the heat dissipation body 112 is mounted on the electronic component 100 (for instance by a screw connection or by a clip, not shown), the interface between the interface structure 108 and the heat dissipation body 112 introduces only a small thermal resistance.

[0141] The foregoing description shows that the interface structure 108 fulfils a plurality of technical functions simultaneously and therefore requires certain mechanical, thermal and electrical properties at the same time. According to the described exemplary embodiments, the interface structure 108 is configured to fulfill all the above described technical functions simultaneously in a proper way when compressibility is in a range between 1% and 20%, in particular at or around 10%. Particularly advantageous effects can be achieved when a value of the breakdown voltage per thickness Vbr multiplied with the thermal conductivity A divided by the square of the Vickers hardness HV is more than 1 kV W mm.sup.3 m.sup.1 K.sup.1 N.sup.2 at room temperature (20 C.)

[0142] The interface structure 108 is configured to have an electric breakdown voltage of about 5.6 kV. This means that the electrical isolation of the interface structure 108 is maintained even when applying a voltage of 5.6 kV across the interface structure 108. In this context it is advantageous that the interface structure 108 has a quite small relative permittivity .sub.r of 4.5. A parasitic capacitance of the interface structure 108 (in combination with the electrically conductive material on both opposing main surfaces thereon) may be sufficiently low at around 40 pF. Thus, electric losses in high-frequency applications are acceptably low.

[0143] The value of the Vickers hardness of the material of the interface structure 108 can be preferably 1 N/mm.sup.2. A maximum indention depth of a Vickers indentor at a measuring force of 1 N may be less than 50 m so that it can be prevented that little scratches or indentations which may occur during ordinary use deteriorate the electric reliability of the electronic component 100. The interface structure 108 may have a Young modulus of 0.6 GPa. A correspondingly limited softness of the interface structure 108 ensures that any microprotrusions or microindentations at a connection surface of the heat removal body 112 to be filled with material of the interface structure 108 upon mounting which decreases a thermal resistance at the interface between the heat removal body 112 and the interface structure 108. Despite of the limited softness, the interface structure 108 shows a scratch resistance at a measuring force of 1 N without effect on the electrically breakdown specification of 5.6 kV. In other words, when a pyramid-shaped diamond indentor is pressed with 1 N against the surface of the interface structure 108 and is moved along this surface, small scratches which might be formed do not cause the electric breakdown voltage to fall below 5.6 kV, which still complies with the high demands of power applications.

[0144] The interface structure 108 may have an intrinsic thermal conductivity of for instance 2 W m.sup.1 K.sup.1 and is therefore capable of significantly contributing to the removal of heat generated during operation of the electronic component 100.

[0145] The mentioned physical parameters of the interface structure 108 may be accomplished by configuring it from a sufficiently soft polymer matrix (for instance of silicone) having embedded therein a certain amount of (for example 90 mass percent) filler particles (for instance from aluminum oxide) for promoting dielectric behaviour and/or thermal conductivity. One or more further additives may be added for fine-tuning the physical parameters of the interface structure 108. A further design parameter for adjusting the desired behaviour is the thickness of the interface structure 108 and the procedure of manufacturing and connecting it to the remainder of the electronic component 100.

[0146] Advantageously, the interface structure 108 consists of a single homogeneous layer of a thickness of 250 m which is integrally formed with the carrier 102 and the encapsulant 106 by compression molding or transfer molding. Due to such a manufacturing, it is possible that material at the border between the interface structure 108 on the one hand and the carrier 102 and the encapsulant 106 on the other hand intermingles or mutually mixes to a certain extent to produce an electronic component 100 with a non-detachable interface structure 108. This further promotes the heat removal capability by reducing the thermal resistance at an interface between the carrier 102 and the interface structure 108 and at an interface between the encapsulant 106 and the interface structure 108. A further improvement of the heat removal capability of the interface structure 108 is obtained since the interface structure 108 extends over an entire bottom surface of the encapsulant 106 and over the entire exposed surface portion of the carrier 102 at a bottom of the electronic component 100. This is a consequence of the molding procedure used for manufacturing the interface structure 108. Integral formation of the interface structure 108 with the carrier 102 and the encapsulant 106 can be further promoted when the connection of the interface structure 108 to the carrier 102 and the encapsulant 106 is triggered by a chemical reaction such as a cross-linking of material of the interface structure 108 (which may be initiated by heat and/or pressure).

[0147] With the configuration of the thermal interface structure 108 according to FIG. 1, a proper trade-off between a sufficiently high electrical breakdown voltage, a sufficiently high capability of removing heat from the electronic chip 104 during operation of the electronic device 100 and a high robustness of the integral thermal interface structure 108 against undesired removal or scratching can be obtained.

[0148] Alternatively to the configuration shown in FIG. 1, it is also possible to attach the thermal interface structure 108 to the base body 112 of the heat dissipation body 114. Such a heat dissipation body 114 equipped with a thermal interface structure 108 may thereafter be connected to an exposed surface of a carrier 102 of an electronic component 100.

[0149] FIG. 2 illustrates a diagram 200 illustrating a dependence of Vickers hardness from a product of thermal conductivity and breakdown voltage per thickness Vbr of a material of an interface structure 108 of an electronic component 100 according to an exemplary embodiment of the invention. Different areas in diagram 200 relates to different values of the parameter MAME as calculated as the product of thermal conductivity and breakdown voltage per thickness Vbr divided by the square of the Vickers hardness.

[0150] The diagram 200 has an abscissa 202 and has an ordinate 204. Along the abscissa 202, the product of the electrical breakdown voltage per thickness Vbr and the thermal conductivity of the thermal interface material (see reference numeral 108 in FIG. 1) is plotted. The ordinate 204 shows the Vickers hardness (at a measuring force of 1 N). In a range 206, it may happen that inappropriate electrical, thermal and mechanical properties are obtained. However, within a range 208, sufficiently appropriate properties with regard to the above-mentioned thermal, mechanical and electrical criteria can be obtained. Thus, thermal interface materials according to exemplary embodiments of the invention may be taken from range 208 where the above-described parameter MAME has a value of larger than 1 kV W mm.sup.3 m.sup.1 K.sup.1 N.sup.2.

[0151] Referring to the lower surface of the interface structure 108 of FIG. 3 (which can form an interface to a carrier 102 such as a lead frame), proper adhesion properties are obtained by the formation of a material compound. This results in an advantageously low heat resistance. At the upper surface of the interface structure 108 of FIG. 3, a dry connection to a heat dissipation body 112 can be accomplished. The interface structure 108 may have a low thermal resistance on a metallic substrate and may have a high breakdown voltage on an electric insulator substrate.

[0152] FIG. 3 illustrates an SEM image 300 of aluminum oxide filled silicone as material for an interface structure 108 of an electronic component 100 according to an exemplary embodiment of the invention. As shown in FIG. 3, the interface structure 108 is arranged on a carrier 102 such as a lead frame (for instance made of copper).

[0153] Thus, the interface structure 108 comprises a matrix 302 of silicone filled with filler particles 304 of aluminum oxide. A mass percentage of the filler particles 304 may be 90%, whereas a mass percentage of the matrix 302 may be 10%. Thus, a relatively small volume is assumed by the silicone matrix 302 providing softness. In contrast to this, a relatively large volume is assumed by the freely selectable filler particles 304 which promote the thermal heat removal capability of the thermal interface material and strengthen the dielectric behaviour thereof.

[0154] Still referring to FIG. 3, a thermal resistivity of below 0.5 K/W (0.40 K/W, 0.37 K/W) could be measured for a TO-247 package with aluminum oxide filled silicone and without using thermal grease, which fulfills strict requirements of modern power packages. This can be compared with the thermal resistivity of conventional hard layer coating having a thermal resistivity of 0.5 K/W with thermal grease and 1.05 K/W without thermal grease. The cross-section of FIG. 3 shows no isolation, because only chip carrier and thermal interface material are visible, and no overlap on the first encapsulation will not lead to an isolation property.

[0155] FIG. 4 illustrates different views of electronic components 100 according to exemplary embodiments of the invention.

[0156] Firstly, FIG. 4 shows that the outline of the thermal interface structure 108 exactly corresponds to the outline of the corresponding main surface of the package or electronic component 100. A through-hole 400 extending through the entire electronic component 100 and therefore also through the thermal interface structure 108 allows to connect the electronic component 100 to a heat dissipation body 112 (not shown in FIG. 4) by a fastening element such as a screw (not shown in FIG. 4). In this context, the above-described softness of the material of the thermal interface structure 108 is advantageous, since it allows a certain compression of the material of the thermal interface structure 108 close to the fastening element during the fastening procedure, and therefore an equilibration of the fastening force and the prevention of undesired air gaps between an exterior surface of the thermal interface structure 108 on the one hand and material of the heat removal body 112 on the other hand.

[0157] Reliability tests for the shown electronic components 100 have proven the applicability of these packages. In particular, FIG. 4 shows three coated TO-247 packages after 96h stress indicating no delamination or voiding.

[0158] FIG. 5 illustrates a plan view of an electronic component 100 according to an exemplary embodiment of the invention having four galvanically insulated separate carrier regions 102A, 102B, 102C, and 102D. FIG. 5 therefore shows an embodiment having a split lead frame as carrier 102. In this embodiment, four separate and mutually electrically insulated electrically conductive lead frame islands are provided as the separate carrier regions 102A, 102B, 102C, and 102D. Each of the separate carrier regions 102A, 102B, 102C, and 102D is configured as a mounting base for a respective electronic chip(s) 104. On the backside of the electronic component 100, interface structure 108 is provided.

[0159] FIG. 6 illustrates a plan view of an electronic component 100 according to another exemplary embodiment of the invention having two galvanically insulated separate carrier regions 102A, 102B. The embodiment of FIG. 6 differs from the embodiment of FIG. 5 in that two rather than four lead frame islands are provided, so that two electronic chips 104 can be mounted on the separate carrier regions 102A, 102B according to FIG. 6. On the backside of the electronic component 100, interface structure 108 is provided.

[0160] FIG. 7 illustrates a plan view of an electronic component 100 according to yet another exemplary embodiment of the invention having separate carrier regions 102A, 102B. Correspondingly, FIG. 8 illustrates a circuit diagram 800 illustrating the electronic functionality of the electronic component 100 according to FIG. 7. In the embodiment of FIG. 7 and FIG. 8, a first electronic chip 104A (which may be embodied as a boost diode) is mounted on carrier region 102A. A second electronic chip 104B (which may be embodied as a boost insulated gate bipolar transistor, IGBT) is mounted on carrier region 102B. A third electronic chip 104C (which may be embodied as an auxiliary diode) is mounted as well on carrier region 102B. Thus, the embodiment of FIG. 7 and FIG. 8 shows an electronic component 100 with a split lead frame having five pins (1, 2, 3, 4, 5) in an electronic application with a power factor correction.

[0161] FIG. 9 illustrates a cross-sectional view of an electronic component 100 according to an exemplary embodiment of the invention having a carrier 102 with three different sections 102E, 102F, and 102G of different thicknesses D1<D2<D3 (alternatively, it is also possible that D1=D2). Thus, the embodiment of FIG. 9 relates to a variant with different thicknesses for the pin portion (see leads thickness D1) and for the actual chip carrier portion (see die pad thickness D3). The package according to FIG. 9 implements different thicknesses of pins (for instance D1=0.6 mm) and actual chip carrier (for instance D3=1.2 mm to 2 mm).

[0162] FIG. 10 illustrates a cross-sectional view of an electronic component 100 according to an exemplary embodiment of the invention having galvanically insulated separate carrier regions 102A, 102B. In the leadless embodiment of FIG. 10, the separate carrier regions 102A, 102B are electrically connected to one another by a bond wire 110. The leadless configuration according to FIG. 10 has electrically conductive contacts for soldering on a printed circuit board opposing to the isolation side.

[0163] It should be noted that the term comprising does not exclude other elements or features and the a or an does not exclude a plurality. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs shall not be construed as limiting the scope of the claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0164] In the following, further aspects are described:

Aspect I: An electronic component, the electronic component comprising: [0165] an electrically conductive carrier; [0166] an electronic chip on the carrier; [0167] an encapsulant encapsulating part of the carrier and the electronic chip; [0168] an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant; [0169] wherein the interface structure is made of a material having a silicone matrix filled with filler particles, in particular filler particles comprising at least one of the group consisting of metal oxide, metal nitride, aluminum oxide, silicon oxide, boron nitride, zirconium oxide, silicon nitride, diamond, and aluminum nitride, with a mass percentage in a range between 75% and 98%, in particular in a range between 90% and 95%.
Aspect II: An electronic component, the electronic component comprising: [0170] an electrically conductive carrier which comprises a plurality of galvanically insulated separate carrier regions; [0171] a plurality of electronic chips each of which being mounted on a respective one of the carrier regions; [0172] an encapsulant encapsulating part of the carrier and the electronic chips; [0173] a common electrically insulating and thermally conductive interface structure covering an exposed surface portion of the carrier regions and a connected surface portion of the encapsulant.
Aspect III: The electronic component according to a previous Aspect, wherein the interface structure has a value of the breakdown voltage per thickness multiplied with the thermal conductivity divided by the square of the Vickers hardness of more than 1 kV W mm.sup.3 m.sup.1 K.sup.1 N.sup.2, in particular of more than 3 kV W mm.sup.3 m.sup.1 K.sup.1 N.sup.2, more particularly of more than 10 kV W mm.sup.3 m.sup.1 K.sup.1 N.sup.2.
Aspect IV: A heat dissipation body, comprising: [0174] a highly thermally conductive base body configured for dissipating heat; [0175] an electrically insulating and thermally conductive interface structure attached to the base body and to be attached to an exposed surface portion of a chip carrier of an electronic component; [0176] wherein the interface structure has a compressibility in a range between 1% and 20%, in particular in a range between 5% and 15%.
Aspect V: A heat dissipation body, comprising: [0177] a highly thermally conductive base body configured for dissipating heat; [0178] an electrically insulating and thermally conductive interface structure attached to the base body and to be attached to an exposed surface portion of a chip carrier of an electronic component; [0179] wherein the interface structure is made of a material having a silicone matrix filled with filler particles, in particular filler particles comprising at least one of the group consisting of metal oxide, metal nitride, aluminum oxide, silicon oxide, boron nitride, zirconium oxide, silicon nitride, diamond, and aluminum nitride, with a mass percentage in a range between 75% and 98%, in particular in a range between 90% and 95%.
Aspect VI: A method of manufacturing an electronic component, the method comprising: [0180] mounting an electronic chip on an electrically conductive carrier; [0181] encapsulating part of the carrier and the electronic chip by an encapsulant; [0182] forming an electrically insulating and thermally conductive interface structure, in particular to cover an exposed surface portion of the carrier and a connected surface portion of the encapsulant, having a compressibility in a range between 1% and 20%, in particular in a range between 5% and 15%.
Aspect VII: A method of manufacturing an electronic component, the method comprising: [0183] mounting an electronic chip on an electrically conductive carrier; [0184] encapsulating part of the carrier and the electronic chip by an encapsulant; [0185] forming an electrically insulating and thermally conductive interface structure, in particular to cover an exposed surface portion of the carrier and a connected surface portion of the encapsulant, wherein the interface structure is made of a material having a silicone matrix filled with filler particles, in particular filler particles comprising at least one of the group consisting of metal oxide, metal nitride, aluminum oxide, silicon oxide, boron nitride, zirconium oxide, silicon nitride, diamond, and aluminum nitride, with a mass percentage in a range between 75% and 98%, in particular in a range between 90% and 95%.
Aspect VIII: A method of manufacturing an electronic component, the method comprising: [0186] mounting each of a plurality of electronic chips on a respective one of a plurality of galvanically insulated separate carrier regions of an electrically conductive carrier; [0187] encapsulating part of the carrier and the electronic chips by an encapsulant; [0188] forming a common electrically insulating and thermally conductive interface structure covering an exposed surface portion of the carrier regions and a connected surface portion of the encapsulant.
Aspect IX: The method according to Aspect VI, wherein the interface structure is formed by at least one of the group consisting of molding, in particular compression molding or transfer molding, stencil printing, and laminating.
Aspect X: The method according to claim VI, wherein the interface structure is connected to the exposed surface portion of the carrier and to the connected surface portion of the encapsulant by chemically modifying the material of the interface structure, in particular by at least one of the group consisting of cross-linking and melting.
Aspect XI: A method of using an interface material according to a previous Aspect for providing an electric isolation and a thermal coupling between a chip carrier of an electronic component and a heat dissipation body.
Aspect XII: A method of using an electrically insulating and thermally conductive interface material for integration with an electronic component, wherein the interface material is made of a material having a silicone matrix filled with filler particles, in particular filler particles comprising at least one of the group consisting of metal oxide, metal nitride, aluminum oxide, silicon oxide, boron nitride, zirconium oxide, silicon nitride, diamond, and aluminum nitride, with a mass percentage in a range between 75% and 98%, in particular in a range between 90% and 95%, for providing an electric isolation and a thermal coupling between a chip carrier of the electronic component and a heat dissipation body.