A METHOD FOR MANUFACTURING A SEMICONDUCTOR SUPER-JUNCTION DEVICE

Abstract

Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

Claims

1. A method for manufacturing a semiconductor super-junction device, comprising: forming a hard mask layer on an n-type epitaxial layer, defining a position of a p-type column through a lithography process, etching the hard mask layer, and forming at least one opening in the hard mask layer, wherein the at least one opening corresponds to the position of the p-type column; etching the n-type epitaxial layer with the hard mask layer as a mask, and forming a first trench in the n-type epitaxial layer, wherein a width of the first trench is larger than a width of one opening of the at least one opening corresponding to the first trench, and the first trench comprises a p-type column region located below the opening corresponding to the first trench and a gate region located on two sides of the p-type column region; forming a sacrificial dielectric layer in the gate region of the first trench; etching the n-type epitaxial layer with the hard mask layer and the sacrificial dielectric layer as a mask, and forming a second trench in the n-type epitaxial layer, wherein the second trench is located below the p-type column region corresponding to the second trench; forming the p-type column in the p-type column region and the second trench, and forming a pn junction structure between the p-type column and the n-type epitaxial layer; and removing the hard mask layer and the sacrificial dielectric layer, and forming a gate dielectric layer and a gate in the gate region of the first trench.

2. The method for manufacturing a semiconductor super-junction device of claim 1, further comprising: forming a p-type body region in the n-type epitaxial layer; and forming an n-type source region in the p-type body region.

3. The method for manufacturing a semiconductor super-junction device of claim 1, wherein the hard mask layer is a laminated layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

4. The method for manufacturing a semiconductor super-junction device of claim 1, wherein an etching method combining an anisotropic etching and an isotropic etching is adopted during forming the first trench through an etching.

5. The method for manufacturing a semiconductor super-junction device of claim 1, wherein the sacrificial dielectric layer is made of a silicon oxide.

6. The method for manufacturing a semiconductor super-junction device of claim 1, wherein a width of the second trench is greater than a width of the p-type column region corresponding to the second trench.

7. The method for manufacturing a semiconductor super-junction device of claim 6, wherein an etching method combining an anisotropic etching and an isotropic etching is adopted during forming the second trench through an etching.

8. The method for manufacturing a semiconductor super-junction device of claim 1, wherein before forming the p-type column, the method further comprises: performing a p-type ion implantation once to form a p-type compensation region below the second trench or to form a p-type compensation region in the n-type epitaxial layer below the second trench and on two sides of the second trench.

9. The method for manufacturing a semiconductor super-junction device of claim 1, wherein the p-type column is made of a p-type polycrystalline silicon.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0023] FIGS. 1-3 are schematic cross-sectional structure diagrams of main structures in a manufacturing process of a semiconductor super junction device in the related art; and

[0024] FIGS. 4-11 are schematic cross-sectional structure diagrams of main structures in a manufacturing process of one embodiment of a method for manufacturing a semiconductor super-junction device provided in the present disclosure.

DETAILED DESCRIPTION

[0025] A technical solution of the present disclosure will now be described in a specific manner in conjunction with the accompanying drawings in embodiments of the present disclosure. Terms such as “having,” “including,” and “includes” as used in the present disclosure do not preclude the presence or addition of one or more other elements, or combinations thereof. Moreover, in order to illustrate specific embodiments of the present disclosure, the schematic drawings are shown exaggerated in thickness of layers and regions of the present disclosure, and the dimensions of the drawings are not representative of actual dimensions.

[0026] FIGS. 4 to 11 are schematic cross-sectional structure diagrams of main structures in a manufacturing process of one embodiment of a method for manufacturing a semiconductor super-junction device provided in the present disclosure.

[0027] Firstly, as shown in FIG. 4, a hard mask layer 30 is formed on a provided n-type epitaxial layer 20, the n-type epitaxial layer 20 is typically a silicon, and the hard mask layer 30 is typically a laminated layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. A position of a p-type column is defined through a photoetching process, then the hard mask layer 30 is etched, at least one opening 31 is formed in the hard mask layer 30, and the at least one opening 31 corresponds to the position of the p-type column, and a number of the openings 31 (namely a number of the p-type columns) in the hard mask layer 30 is determined by a specification of the designed semiconductor super-junction device. Two openings 31 are shown in the embodiment of the present disclosure by way of example only.

[0028] Next, as shown in FIG. 5, the n-type epitaxial layer 20 is etched with the hard mask layer 30 as a mask, a first trench 32 is formed in the n-type epitaxial layer 20, the first trenches 32 are in one-to-one correspondence with the openings in the hard mask layer 30, and the first trench 32 includes a p-type column region 32a located below a corresponding opening and a gate region 32b located on two sides of the p-type column regions 32a. When the first trench 32 is formed through an etching, a method combining an anisotropic etching and an isotropic etching is selected, for example, the p-type column region 32a of the first trench 32 is formed through an anisotropic etching method, and then the gate region 32b of the first trench 32 is formed through an isotropic etching method.

[0029] Next, as shown in FIG. 6, a sacrificial dielectric layer 40 is formed in a gate region of the first trench, and the sacrificial dielectric layer 40 is typically a silicon oxide. The method includes following steps: firstly, a layer of silicon oxide is formed through a depositing or oxidizing, and then the deposited silicon oxide is etched back. When the silicon oxide is formed through the depositing, a whole first trench may be filled with the silicon oxide, or the whole first trench may not be filled with the silicon oxide, but the gate region of the first trench is filled with the silicon oxide.

[0030] Next, as shown in FIG. 7, the n-type epitaxial layer 20 is etched with the hard mask layer 30 and the sacrificial dielectric layer 40 as masks, and a second trench 34 located below the first trench is formed in the n-type epitaxial layer 20. Optionally, as shown in FIG. 8, a width of the second trench 34 may be greater than a width of a corresponding p-type column region, and correspondingly, when the second trench 34 is formed through an etching, an etching method combining an anisotropic etching and an isotropic etching may be adopted, exemplarily, the anisotropic etching method may be adopted firstly to perform the etching, and the isotropic etching method may be adopted secondly to perform the etching, so that the width of the second trench 34 is increased, and thus a width of the n-type epitaxial layer between adjacent second trenches 34 is reduced.

[0031] Next, as shown in FIG. 9, a p-type column 23 is formed in the p-type column region and the second trench, and the hard mask layer and the sacrificial dielectric layer are removed. A pn junction structure is formed between the p-type column 23 and the n-type epitaxial layer 20, and the p-type column 23 may be made of a p-type polycrystalline silicon and is typically formed through an epitaxial process. Optionally, a p-type ion implantation may be performed once before the p-type column 23 is formed so as to form a p-type compensation region below the second trench or in the n-type epitaxial layer below the second trench and on two sides of the second trench, which achieves a better charge balance effect.

[0032] Next, as shown in FIG. 10, a gate dielectric layer 21 and a gate 22 are formed in the gate region of the first trench, and the gate 22 is isolated from the p-type column 23 by the gate dielectric layer 21.

[0033] Next, as shown in FIG. 11, a p-type body region 24 is formed in the n-type epitaxial layer 20, and an n-type source region 25 is formed in the p-type body region 24.

[0034] Structures such as an interlayer dielectric layer, a metal layer are formed according to a conventional process so as to obtain the semiconductor super-junction device.