LTPS-based CMOS component and method for manufacturing the same

Abstract

Disclosed are an LTPS-based CMOS component and a method for manufacturing the same. The CMOS component includes an NMOS type LTPS. PN junctions are provided in an NMOS type LTPS channel to reduce the movement speed of electrons in the channel, so that hot electron effects can be avoided. The LTPS-based CMOS component can reduce the movement speed of electrons and avoid hot electron effects.

Claims

1. A Low Temperature Poly-silicon (LTPS)-based complementary metal oxide semiconductor component, comprising: a channel layer, wherein a negative metal oxide semiconductor (NMOS)-type LTPS channel is located in the channel layer, a P-type heavily doped region is provided in a middle of the NMOS-type LTPS channel, and an N-type heavily doped region is provided at each end of the NMOS-type LTPS channel; a buffer layer, arranged under the channel layer, wherein the buffer layer further comprises a silicon nitride (SiNx) buffer layer and a silicon oxide (SiOx) buffer layer, and the silicon oxide buffer layer is in contact with the channel layer; a gate insulating layer, arranged on the channel layer and covering the entire channel layer and exposed portions of the buffer layer; a gate layer, arranged on the gate insulating layer, being narrower than the NMOS-type LTPS channel, and surrounded by a dielectric layer; the dielectric layer, arranged on the gate layer and exposed portions of the gate insulating layer; and a source electrode and a drain electrode, arranged on the dielectric layer, wherein the source electrode is connected to one end of the NMOS-type LTPS channel, and the drain electrode is connected to the other end of the NMOS-type LTPS channel by means of via holes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings provide further understandings of the present disclosure and constitute one part of the description. The drawings are used for interpreting the technical solutions of the present disclosure together with the embodiments, not for limiting the present disclosure. In the drawings:

(2) FIG. 1a schematically shows a component structure corresponding to a step for fabrication of a PMOS LTPS according to one embodiment of the present disclosure;

(3) FIG. 1b schematically shows a component structure corresponding to the step for fabrication of an NMOS LTPS according to one embodiment of the present disclosure;

(4) FIG. 1c schematically shows a component structure corresponding to the step for P-type heavy doping according to one embodiment of the present disclosure;

(5) FIG. 1d schematically shows a component structure corresponding to the step for fabrication of a gate insulating layer according to one embodiment of the present disclosure;

(6) FIG. 1e schematically shows a component structure corresponding to the step for fabrication of a gate layer according to one embodiment of the present disclosure;

(7) FIG. 1f schematically shows a component structure corresponding to the step for fabrication of a dielectric layer according to one embodiment of the present disclosure;

(8) FIG. 2 schematically shows a component structure corresponding to the step for fabrication of a source and a drain according to one embodiment of the present disclosure;

(9) FIG. 3a schematically shows a component structure corresponding to the step for fabrication of a PMOS LTPS according to one embodiment of the present disclosure;

(10) FIG. 3b schematically shows a component structure corresponding to the step for P-type heavy doping of a channel according to one embodiment of the present disclosure;

(11) FIG. 3c schematically shows a component structure corresponding to the step for fabrication of an NMOS LTPS according to one embodiment of the present disclosure;

(12) FIG. 3d schematically shows a component structure corresponding to the step for performing N-type light doping on an NMOS according to one embodiment of the present disclosure;

(13) FIG. 3e schematically shows a component structure corresponding to the step for an N-type heavy doping process according to one embodiment of the present disclosure;

(14) FIG. 3f schematically shows a component structure corresponding to the step for a P-type heavy doping process according to one embodiment of the present disclosure; and

(15) FIG. 4 schematically shows a component structure corresponding to the step for fabrication of a source and a drain according to one embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(16) The present disclosure will be explained in details with reference to the embodiments and the accompanying drawings, whereby it can be fully understood how to solve the technical problem by the technical means according to the present disclosure and achieve the technical effects thereof, and thus the technical solution according to the present disclosure can be implemented. As long as there is no structural conflict, all the technical features mentioned in all the embodiments may be combined together in any manner, and the technical solutions obtained in this manner all fall within the scope of the present disclosure.

(17) In order to solve the problem of the complicated LDD process in the prior art, the present disclosure provides a CMOS component which prevents hot carrier effects of NMOS type LTPS.

(18) The CMOS component comprises an NMOS type LTPS. An NMOS type LTPS channel is provided therein with PN junctions to reduce movement speed of electrons in the channel, so as to avoid hot electron effects.

(19) FIG. 2 schematically shows a structure of an NMOS type LTPS according to one embodiment of the present disclosure. As shown in FIG. 2, the NMOS type LTPS comprises in order from bottom to top: a buffer layer which is formed on a glass substrate GLA, the buffer layer comprising a SiNx layer provided on the glass substrate GLA and a SiOx layer provided on the SiNx layer; an NMOS type LTPS channel layer which is provided on the buffer layer, the channel layer comprising an N-type channel NSi and P-type heavily doped regions P+-Si which are located at both ends of the channel and are respectively in communication with a source and a drain; a gate insulating layer GI which is provided on the NMOS type LTPS channel layer and exposed portions of the buffer layer; a gate layer which is provided on the gate insulating layer for forming a gate pattern G; a dielectric layer ILD which is provided on the gate layer and exposed portions of the gate insulating layer GI; and a source S and a drain D which are provided on the dielectric layer ILD and are respectively in communication with both ends of the NMOS type LTPS channel.

(20) Specifically, as shown in FIG. 2, P-type heavily doped regions P+-Si rather than N-type heavily doped regions are provided in regions where the source and the drain are in contact with the NMOS type LTPS, so that PN junctions are formed between the P-type heavily doped regions and the NMOS type LTPS channel. In this way, a structure of a P+NP+ type transistor is formed in a channel region of the NMOS type LTPS. P+ represents P-type heavy doping, and N+ represents N-type heavy doping. When a current flows from the drain D to the source 5, a diode formed by P+N is turned on in a forward direction and the current is unimpeded. However, NP+ forms a zener diode. An advantage of a zener diode is the formation of a small depletion region, and when electrons pass through the depletion region, the movement speed thereof is slowed down. The electrons can pass through the depletion region, but do not damage the device like an avalanche diode. This solves the problem of hot electron effects caused by the high movement speed of the electrons, and solves the problem of a source and a drain being in contact with an LTPS. Thus, two photomasks corresponding to an N-type heavy doping N+ and an N-type light doping N can be saved, while an LDD structure is formed.

(21) FIG. 4 schematically shows a structure of an NMOS type LTPS according to another embodiment of the present disclosure. As shown in FIG. 4, a P-type heavily doped region is provided in a channel region of the NMOS type LTPS, so that PN junctions are formed between the P-type heavily doped region and the channel region of the NMOS type LTPS. By performing a P-type heavy doping process in the middle of the NMOS type LTPS channel, an NP+N transistor structure is formed. In the structure, a P+ type LTPS can be compared to a hurdle and the movement speed of electrons may be reduced to a certain extent when electrons get across the hurdle, Thus, hot electron effects can be avoided and photomasks required in N-type light doping N can be saved. Other structures in the channel region of the NMOS type LTPS are the same as those in FIG. 2, and are not described here in detail.

(22) In one embodiment of the present disclosure, the LTPS-based CMOS component further comprises a PMOS type LTPS. The PMOS type LTPS and the NMOS type LTPS form a complete CMOS component. As shown in FIGS. 2 and 4, the PMOS type LTPS comprises in order from bottom to top: a buffer layer which is provided on a glass substrate GLA, the buffer layer comprising a SiNx layer provided on the glass substrate GLA and a SiOx layer provided on the SiNx layer; a PMOS type LTPS channel layer which is provided on the buffer layer, the channel layer comprising a P-type channel PSi and P-type heavily doped regions P+Si which are located at both ends of the channel and are respectively in communication with a source and a drain; a gate insulating layer GI which is provided on the PMOS type LTPS channel layer and exposed portions of the buffer layer; a gate layer which is provided on the gate insulating layer for forming a gate pattern G; a dielectric layer ILD which is formed on the gate layer and exposed portions of the gate insulating layer GI; and a source S and drain D which are provided on the dielectric layer ILD and are respectively in communication with both ends of the channel of the PMOS type LTPS.

(23) According to another aspect of the present disclosure, a method for manufacturing an LTPS-based CMOS component is further provided. The method specifically comprises the following steps.

(24) First, a buffer layer is formed on a glass substrate. Specifically, a SiNx layer is formed on the substrate GLA by CVD (Chemical Vapor Deposition), and then a SiOx layer is formed on the SiNx layer.

(25) Next, a PMOS type LTPS channel layer and an NMOS type LTPS channel layer are formed on the buffer layer. The PMOS type LTPS channel layer comprises a P-type channel PSi, and P-type heavily doped regions P+-Si which are located at both ends of the P-type channel PSi and are respectively in communication with a source and a drain. The NMOS type LTPS channel layer comprises an N-type channel NSi, and P-type heavily doped regions P+-Si at both ends of the channel and in communication with a source and a drain.

(26) Specifically, in the formation of the PMOS type LTPS channel layer and the NMOS type LTPS channel layer, an amorphous silicon (a-Si) film is first formed on the buffer layer by CVD. Then, the a-Si film is exposed to light and etched to form an a-Si island pattern, and the a-Si island pattern is crystallized by ELA to obtain a P-type LTPS, as shown in FIG. 1a. Next, the obtained LTPS is coated with a photoresist and exposed to light, and an NMOS region of the LIPS is lightly n-doped, and then the photoresist is removed to form an NMOS type LTPS pattern (NMOS type LTPS channel layer), as shown in FIG. 1b. Next, the LTPS is again coated with a photoresist and exposed to light, and both ends of the channel of the PMOS type LTPS channel layer and both ends of the channel of the NMOS type LTPS channel layer are heavily p-doped, i.e., both ends of the a-Si silicon island pattern are heavily p-doped. And then, the photoresist is removed to form P+-Si patterns, as shown in FIG. 1c.

(27) Next, a gate insulating layer GI is formed on the NMOS type LTPS channel layer, the PMOS type LTPS channel layer, and exposed portions of the buffer layer by CVD, as shown in FIG. 1d.

(28) Next, a gate layer is formed on the gate insulating layer GI. Specifically, a metal film is formed on the gate insulating layer GI by the physical vapor deposition (PVD), and then a gate is formed by means of exposure and development, as shown in FIG. 1e.

(29) Next, a dielectric layer ILD is formed on the gate layer and exposed portions of the gate insulating layer, and via holes are formed by etching on the dielectric layer for connecting the P-type heavily doped regions at both ends of the channel in the NMOS type channel layer and connecting the P-type heavily doped regions at both ends of the channel in the PMOS type LTPS channel layer. Specifically, the dielectric layer is formed by CVD, and then IDL layer patterns are formed by exposure and dry etching, as shown in FIG. 1f.

(30) Finally, a source and a drain of the CMOS component are formed on the dielectric layer IDL, and the source and the drain are respectively in communication with corresponding P-type heavily doped regions by means of the via holes. Specifically, a metal film is formed by PVD first, and then a source pattern and a drain pattern are respectively formed by exposure and development. The source and the drain are in communication with a source region and a drain region corresponding to the NMOS type LTPS and PMOS type LTPS by means of the via holes, as shown in FIG. 2.

(31) According to further another aspect of the present disclosure, another method for manufacturing an LTPS-based CMOS component is further provided. The method specifically comprises the following steps.

(32) First, a buffer layer is formed on a glass substrate GLA. Specifically, a SiNx layer is formed on the substrate GLA by CVD, and then a SiOx layer is formed on the SiNx layer.

(33) Next, PMOS type EPS channel layers are formed in a corresponding PMOS region and a corresponding NMOS region on the buffer layer, as shown in FIG. 3a.

(34) Next, an inner region of a channel in the PMOS type LTPS channel layer in the NMOS region is heavily p-doped to obtain a P-type heavily doped region P+-Si, as shown in FIG. 3b. Specifically, a photoresist PR is applied to the PMOS type LTPS channel layers. A region of the channel in the PMOS type LTPS channel layer in the NMOS region, preferably a middle region of the channel, is irradiated with a semi-transparent photomask, to remove the photoresist in the region, and then the region where the photoresist is removed is heavily p-doped to obtain a P-type heavily doped LTPS.

(35) Next, the photoresist corresponding to the NMOS is etched away by dry etching, and the photoresist corresponding to PMOS is reserved, as shown in FIG. 3c.

(36) Next, the LTPS channel in the NMOS region is lightly n-doped, and then the photoresist is removed to form an NMOS type LTPS pattern (NMOS type LTPS channel layer), as shown in FIG. 3d.

(37) Next, the process of photoresist coating and exposure is further performed, and both ends of an a-Si silicon island pattern of the LTPS in the NMOS region is heavily n-doped, and then the photoresist is removed to form N+-Si patterns, as shown in FIG. 3e.

(38) Next, the process of photoresist coating and exposure is further performed, and both ends of the a-Si silicon island pattern of the LTPS in the PMOS region is heavily p-doped, and then the photoresist is removed to for a P+-Si patterns, as shown in FIG. 3f.

(39) Next, a gate insulating layer GI is formed on the NMOS type LTPS channel layer, the PMOS type LTPS channel layer, and exposed portions of the buffer layer by CVD.

(40) Next, a gate layer is formed on the gate insulating layer GI. Specifically, a metal film is formed on the gate insulating layer GI by PVD, and then a gate is formed by exposure and development.

(41) Next, a dielectric layer ILD is formed on the gate layer and exposed portions of the gate insulating layer, and via holes are formed by etching on the dielectric layer for connecting the P-type heavily doped regions at both ends of the channel in the NMOS type channel layer and connecting the P-type heavily doped regions at both ends of the channel in the PMOS type TPS channel layer. Specifically, the dielectric layer is formed by CVD, and IDL layer patterns are formed by exposure and dry etching.

(42) Finally, a source and a drain of the CMOS component are formed on the dielectric layer, and the source and the drain are respectively in communication with corresponding P-type heavily doped regions by means of the via holes. Specifically, a metal film is formed by PVD, and then a source pattern and a drain pattern are respectively formed by exposure and development. The source and the drain are in communication with a source region and a drain region respectively corresponding to the NMOS type LTPS and the PMOS type LTPS by means of the via holes, as shown in FIG. 4.

(43) The step of performing an N-type heavy doping process to form the N+Si pattern may be swapped with the step of performing a P-type heavily doping process to form the P+Si pattern.

(44) The above embodiments are described only for better understanding, rather than restricting the present disclosure. Any person skilled in the art can make amendments to the implementing forms or details without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure shall be determined by the scope as defined in the claims.