Bipolar junction transistor and method for fabricating the same

Abstract

A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.

Claims

1. A method for fabricating bipolar junction transistor (BJT), comprising: providing a substrate having an emitter region, a base region, and a collector region; forming fin-shaped structures on the substrate; performing a first implantation process to form a first well region in the base region; forming a shallow trench isolation (STI) between the emitter region and the base region; performing a second implantation process to form a first region in the fin-shaped structures on the emitter region and a second region under the first region, wherein a bottom surface of the first well region is lower than a bottom surface of the first region; and performing a thermal treatment to diffuse dopants from the first region downward into the second region to form a second well region, wherein the first well region and the second well region comprise different concentrations.

2. The method of claim 1, further comprising: performing a third implantation process to form a deep well region in the substrate under the fin-shaped structures; and performing the first implantation process.

3. The method of claim 2, further comprising performing a fourth implantation process between the first implantation process and the second implantation process to form a third well region in the collector region.

4. The method of claim 3, wherein the first well region and the second well region comprise a first conductive type and the deep well region and the third well region comprise a second conductive type.

5. The method of claim 4, wherein the first conductive type comprises p-type and the second conductive type comprises n-type.

6. The method of claim 1, wherein the first region is a doped region and the second region is an undoped region.

7. The method of claim 2, further comprising: forming a gate dielectric layer on the fin-shaped structures; performing the second implantation process; and forming a gate structure on each of the emitter region, the base region, and the collector region.

8. The method of claim 1, wherein a concentration of the second well region is lower than a concentration of the first well region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1-7 illustrate a method for fabricating a BJT according to an embodiment of the present invention.

DETAILED DESCRIPTION

(2) Referring to FIGS. 1-7, FIGS. 1-7 illustrate a method for fabricating a BJT according to an embodiment of the present invention. As shown in FIG. 1, a substrate 12, such as a silicon substrate or a silicon-on-insulator (SOI) substrate is first provided, multiple fin-shaped structures 14 are formed on the substrate 12, and an emitter region 16, a base region 18, and a collector region 20 are defined on the substrate 12. In this embodiment, the emitter region 16 is preferably disposed on the central fin-shaped structure 14, the base region 18 is defined on the fin-shaped structures 14 adjacent to two sides of the emitter region 16, and the collector region 20 is defined on the fin-shaped structures 14 adjacent to two sides of the base region 18. It should be noted that even though this embodiment pertains to the fabrication of a non-planar FET device such as FinFET device, it would also be desirable to apply the following process to a planar FET device, which is also within the scope of the present invention.

(3) According to an embodiment of the present invention, the fin-shaped structure 14 could be obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained.

(4) Alternatively, the fin-shaped structure 14 could also be obtained by first forming a patterned mask (not shown) on the substrate, 12, and through an etching process, the pattern of the patterned mask is transferred to the substrate 12 to form the fin-shaped structure. Moreover, the formation of the fin-shaped structure could also be accomplished by first forming a patterned hard mask (not shown) on the substrate 12, and a semiconductor layer composed of silicon germanium is grown from the substrate 12 through exposed patterned hard mask via selective epitaxial growth process to form the corresponding fin-shaped structure. These approaches for forming fin-shaped structure are all within the scope of the present invention.

(5) Next, an ion implantation process 22 is conducted to implant dopants having second conductive type (such as n-type) into the substrate 12 under the fin-shaped structures 14 on the emitter region 16, base region 18, and collector region 20 for forming a deep well region such as a deep n-well 24.

(6) Next, as shown in FIG. 2, another ion implantation process 26 is conducted to implant dopants having first conductive type (such as p-type) into the fin-shaped structures 14 on the base region 18 and part of the substrate 12 under the fin-shaped structures 14 for forming at least a well region such as a p-well 28. Preferably, a patterned mask (not shown) is formed to cover the emitter region 16 and the collector region 20 before the implantation process 26 is conducted so that p-type dopants or ions would only be injected into the fin-shaped structures 14 and part of the substrate 12 on the base region 18 but not into the fin-shaped structures 14 on the emitter region 16 and the collector region 20.

(7) Next, as shown in FIG. 3, another ion implantation process 30 is conducted to implant dopants having second conductive type (such as n-type) into the fin-shaped structures 14 on the collector region 20 as well as part of the substrate 12 directly under the fin-shaped structures 14 on the collector region 20 for forming at least a well region such as n-well 32. Similar to the formation of the p-well 28, it would be desirable to form a patterned mask (not shown) to cover the emitter region 16 and the base region 18 before the ion implantation process 30 is conducted so that n-type dopants or ions would only be injected into the fin-shaped structures 14 and part of the substrate 12 on the collector region 20 but not into the fin-shaped structures 14 on the emitter region 16 and the base region 18. Next, a thermal treatment process could be conducted to activate the dopants implanted into each of the well regions including the deep n-well 24, the p-well 28, and the n-well 32. Preferably, the fin-shaped structure 14 on the emitter region 16 still remains to be an undoped region at this stage.

(8) Next, as shown in FIG. 4, a shallow trench isolation (STI) 62 made of dielectric material including but not limited to for example silicon oxide could be formed around the fin-shaped structures 14, a gate dielectric layer 34 is formed in the fin-shaped structures 14 on each region, and an ion implantation process 36 is conducted to implant dopants having first conductive type (such as p-type) into the fin-shaped structure 14 on the emitter region 16 for forming a first region 38 and a second region 40 directly under the first region 38. Preferably, the dosage and energy of the ion implantation process 36 are both less than the dosage and energy used in the ion implantation process 26 so that the first region 38 preferably becomes a doped region with implanted p-type dopants while the second region 40 remains to be an undoped region and the depth of the first region 38 is preferably less than the depth of the p-well 28 on the base region 18.

(9) Next, a thermal treatment process is conducted to diffuse the dopants in the first region 38 downward and at the same time diffuse the dopants from the adjacent p-well 28 to the second region 40 for forming another p-well 42. Specifically, the p-well 42 is preferably formed by dopants diffused from two paths, which preferably includes p-type dopants diffused from the first region 38 following the direction of the down arrow downward as well as p-type dopants diffused from the adjacent p-well 28 on the base region 18 following the direction of the left and right arrows through the substrate 12 under the fin-shaped structures 14 to the second region 40 on the emitter region 16.

(10) In this embodiment, the concentration of the p-well 42 formed on the emitter region 16 is preferably less than the concentration of p-well 28 on the base region 18. For instance, the concentration of the p-well 42 is preferably between 310.sup.13 ions/cm.sup.2 to 410.sup.13 ions/cm.sup.2 and the concentration of the p-well 28 is preferably between 110.sup.14 ions/cm.sup.2 to 1.2110.sup.14 ions/cm.sup.2. In contrast to the conventional BJT typically having p-wells with equal concentration on both emitter region and base region, the present invention preferably implants dopants of different concentration into the emitter region 16 and base region 18 respectively under different stages. This forms a p-well 28 with substantially higher concentration in the base region 18 and at the same time forms a p-well 42 with relatively lower concentration in the emitter region 16 to improve the performance of the BJT device.

(11) Next, as shown in FIG. 5, at least a gate structure or dummy gate 44 is formed on each of the emitter region 16, base region 18, and collector region 20. In this embodiment, the formation of the dummy gates 44 could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process. Since this embodiment pertains to a high-k last approach, a gate material layer 46 made of polysilicon and a selective hard mask could be formed sequentially on the substrate 12, and a pattern transfer process is then conducted by using a patterned resist (not shown) as mask to remove part of the gate material layer 46 and part of the gate dielectric layer 34 through single or multiple etching processes. After stripping the patterned resist, dummy gates 44 or gate structures each composed of a patterned gate dielectric layer 34 and patterned gate material layer 46 are formed on the substrate 12.

(12) Next, at least a spacer 48 is formed on the sidewalls of each of the dummy gates 44, source/drain regions 50 and/or epitaxial layer (not shown) are formed in the fin-shaped structure 14 adjacent to two sides of the spacers 48, and selective silicide layers (not shown) could be formed on the surface of the source/drain regions 50. In this embodiment, each spacer 48 could be a single spacer or a composite spacer, such as a spacer including but not limited to for example an offset spacer (not shown) and a main spacer (not shown). Preferably, the spacer 48 in this embodiment includes dielectric material such as silicon nitride. Nevertheless, the spacers 48 could also be made of material including but not limited to for example SiO.sub.2, SiN, SiON, SiCN, or combination thereof.

(13) Moreover, the source/drain regions 50 on the emitter region 16 and the collector region 20 preferably include same conductive type such as n-type dopants and the epitaxial layers disposed on the emitter region 16 and the collector region 20 preferably include silicon phosphide (SiP). The source/drain region 50 on the base region 18 on the other hand preferably includes p-type dopants and the epitaxial layer disposed on the base region 18 preferably includes silicon germanium (SiGe).

(14) Next, as shown in FIG. 6, a contact etch stop layer (CESL) (not shown) could be formed on the surface of the fin-shaped structures 14 and covering the dummy gates 44, and an interlayer dielectric (ILD) layer 52 is formed on the CESL. Next, a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the ILD layer 52 and part of the CESL for exposing the gate material layer 46 made of polysilicon so that top surface of the gate material layer 46 is even with the top surface of the ILD layer 52.

(15) Next, a replacement metal gate (RMG) process is conducted to transform the dummy gates 44 into metal gates. For instance, as shown in FIG. 7, the RMG process could be accomplished by first performing a selective dry etching or wet etching process using etchants including but not limited to for example ammonium hydroxide (NH.sub.4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 46 for forming recesses (not shown) in the ILD layer 52. Next, a high-k dielectric layer 54, a work function metal layer 56, and a low resistance metal layer 58 are formed in the recesses, and a planarizing process such as CMP is conducted to remove part of low resistance metal layer 58, part of work function metal layer 56, and part of high-k dielectric layer 54 to form metal gate 60. In this embodiment, each of the metal gates 60 fabricated through high-k last process of a gate last process preferably includes an interfacial layer or gate dielectric layer 34, a U-shaped high-k dielectric layer 54, a U-shaped work function metal layer 56, and a low resistance metal layer 58.

(16) In this embodiment, the high-k dielectric layer 54 is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer 54 may be selected from hafnium oxide (HfO.sub.2), hafnium silicon oxide (HfSiO.sub.4), hafnium silicon oxynitride (HfSiON), aluminum oxide (A1.sub.2O.sub.3), lanthanum oxide (La.sub.2O.sub.3), tantalum oxide (Ta.sub.2O.sub.5), yttrium oxide (Y.sub.2O.sub.3), zirconium oxide (ZrO.sub.2), strontium titanate oxide (SrTiO.sub.3), zirconium silicon oxide (ZrSiO.sub.4), hafnium zirconium oxide (HfZrO.sub.4), strontium bismuth tantalate (SrBi.sub.2Ta.sub.2O.sub.9, SBT), lead zirconate titanate (PbZr.sub.xTi.sub.1-xO.sub.3, PZT), barium strontium titanate (Ba.sub.xSr.sub.1-xTiO.sub.3, BST) or a combination thereof.

(17) In this embodiment, the work function metal layer 56 is formed for tuning the work function of the metal gate in accordance with the conductivity of the device. For an NMOS transistor, the work function metal layer 56 having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the work function metal layer 56 having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer 56 and the low resistance metal layer 58, in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer 58 may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof.

(18) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.