METHOD FOR 3D WAVEFORM MAPPING OF FULL-PARALLEL STRUCTURE
20190392551 ยท 2019-12-26
Assignee
Inventors
- Wuhuang Huang (Chengdu, CN)
- Pan WANG (Chengdu, CN)
- JUN JIANG (CHENGDU, CN)
- Peng YE (Chengdu, CN)
- Kuojun YANG (Chengdu, CN)
- Lianping GUO (Chengdu, CN)
- Hao ZENG (Chengdu, CN)
- Shuo Wang (Chengdu, CN)
- Jian GAO (Chengdu, CN)
Cpc classification
G06F3/0659
PHYSICS
G06F3/0604
PHYSICS
G01R13/206
PHYSICS
International classification
G01R13/02
PHYSICS
Abstract
The present invention provides a method for 3D waveform mapping of full-parallel structure, first, a 3D waveform mapping database is created according to the size of a 3D waveform image, the number of bits of probability value and the ADC's resolution of data acquisition module, then the 3D waveform mapping database is divided into M.sub.tM.sub.a independent mapping storage areas along the time axis and the amplitude axis, and each independent mapping storage area is assigned a RAM, then RAMs are selected and addresses are calculated based on the sampling values and the structure of created 3D waveform mapping database, finally, parallel mappings are performed simultaneously on the time axis and the amplitude axis according to the selected RAMs and calculated addresses. Thus, the mapping time are shorten, especially in vector mapping mode, several RAMs are used for mapping, so the WCR of DSO is improved.
Claims
1. A method for 3D waveform mapping of full-parallel structure, comprising: (1). creating a 3D waveform mapping database, where the size of the 3D waveform mapping database is L2.sup.NB/8 (byte), L and 2.sup.N are respectively the length and the width of a 3D waveform image, B is the number of bits of probability value, N is the ADCs resolution of a data acquisition module; (2). dividing the 3D waveform mapping database into M.sub.t vertical mapping storage areas along the time axis and M.sub.a horizontal mapping storage areas along the amplitude axis, thus M.sub.tM.sub.a independent mapping storage areas are obtained, where an independent mapping storage area is represented by S.sub.ij, i is the serial number of the independent mapping storage area on the time axis, i=0, 1, . . . , M.sub.t1, j is the serial number of the independent mapping storage area on the amplitude axis, j=0, 1, . . . , M.sub.a1; assigning a random access memory (RAM) for each independent mapping storage area, where the size of the RAM is W.sub.dataT.sub.addr, W.sub.data is the bit width of data of the RAM, and W.sub.data=B, T.sub.addr is the address length of the RAM, and T.sub.addr=(L2.sup.N)/(M.sub.tM.sub.a), the RAM for independent mapping storage area S.sub.ij is represented by R.sub.ij; (3). 3D waveform mapping based on full-parallel structure 3.1). point mapping 3.1.1). initializing serial number k of read to 0; 3.1.2). parallel reading out M.sub.t sampling values from a FIFO memory in which the sampling values acquired by the data acquisition module are stored, then selecting a RAM R.sub.ij for each sampling value Y.sub.kl, l=0, 1, . . . , M.sub.t1, according to the following equations:
i=l, j=Y.sub.kl/M.sub.a; where l is the serial number of sampling value Y.sub.kl, is the operator of downward rounding; 3.1.3). calculating a physical address A.sub.kl for each sampling value Y.sub.kl, l=0, 1, . . . , M.sub.t1 according to the following equation:
i=l, h=(2.sup.N1Y.sub.kl,max)/M.sub.a, g=(2.sup.N1Y.sub.kl,min)/M.sub.a then selecting RAMs between RAM R.sub.ih and RAM R.sub.ig for each pairs of maximum values and minimum values Y.sub.kl,max, Y.sub.kl,min; 3.2.4). calculating a physical address A.sub.kl,max for each maximum value Y.sub.kl,max and a physical address A.sub.kl,max for each maximum value Y.sub.kl,max, l=0, 1, . . . , M.sub.t1, according to the following equations:
2. A method for 3D waveform mapping of full-parallel structure of claim 1, further comprising: (4). reading out each probability value from each RAM, and reformulating it in term of percentage, then converting it into a luminance value H according to the following equations:
Description
BRIEF DESCRIPTION OF THE DRAWING
[0040] The above and other objectives, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
[0041]
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[0047]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0048] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the similar modules are designated by similar reference numerals although they are illustrated in different drawings. Also, in the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may obscure the subject matter of the present invention.
Embodiment
[0049]
[0050] In one embodiment, As shown in
[0051] Step S1: creating a 3D waveform mapping database, where the size of the 3D waveform mapping database is L2.sup.NB/8 (byte), L and 2.sup.N are respectively the length and the width of a 3D waveform image, B is the number of bits of probability value, N is the ADC's resolution of a data acquisition module.
[0052] As shown in
[0053] Step S2: as shown in
[0054] As shown in
[0055] In one embodiment, M.sub.t=8, M.sub.a=4, L=1024, N=8, thus the 3D waveform mapping database is divided into 32 independent mapping storage areas, L=1024, N=8, thus, the address length of the RAM T.sub.addr=(L2.sup.N)/(M.sub.tM.sub.a)=8192. The bit width of data of the RAM W.sub.data=B=8, the size of the RAM is 81928 (bit).
[0056] Step S3: 3D waveform mapping based on full-parallel structure
[0057] The 3D waveform display of DSO has two modes: point display and vector display, correspondingly, the waveform mapping has two modes: point mapping and vector mapping. point mapping and vector mapping in present invention are respectively described in details as below,
[0058] Step S3.1: point mapping
[0059] Step S3.1.1: initializing serial number k of read to 0;
[0060] Step S3.1.2: parallel reading out M.sub.t sampling values from a FIFO memory in which the sampling values acquired by the data acquisition module are stored, then selecting a RAM R.sub.ij for each sampling value Y.sub.kl, l=0, 1, . . . , M.sub.t1, according to the following equations:
i=l, j=Y.sub.kl/M.sub.a;
[0061] where l is the serial number of sampling value Y.sub.kl, is the operator of downward rounding.
[0062] Step S3.1.3: calculating a physical address A.sub.kl for each sampling value Y.sub.kl, l=0, 1, . . . , M.sub.t1 according to the following equation:
[0063] where % is the operator of Mod.
[0064] In one embodiment, the sampling values of the k.sup.th read is Y.sub.kl, the RAM for sampling value Y.sub.kl is R.sub.ij, where the i=l, j=Y.sub.kl/4, k=0, 1, 2 . . . 127, l=0, 1, 2, . . . , 7, the physical address for sampling value Y.sub.kl is [2.sup.8/4(k+1)1](Y.sub.kl % 4).
[0065] Step S3.1.4: parallel updating the probability values of the storage units for the M.sub.t sampling values: for each sampling value Y.sub.kl, reading out a probability value (initial value is 0) from a storage unit according to physical address A.sub.ki in RAM R.sub.ij, and adding 1 to the probability value, then writing the added probability value back to the storage unit.
[0066] Step S3.1.5: setting serial number k of read to k+1, and returning to step S3.1.5, until L sampling values have been mapped.
[0067] Step S3.1.6: returning to step S3.1.1, until a screen refresh signal arrives.
[0068] Step S3.2: vector mapping
[0069] Step S3.2.1: initializing serial number k of read to 0;
[0070] Step S3.2.2: when in normal sampling mode, parallel reading out M.sub.t sampling values from a FIFO memory in which the sampling values acquired by the data acquisition module are stored, then selecting M.sub.t pairs of maximum values and minimum values Y.sub.kl,max, Y.sub.kl,min, l=0, 1, . . . , M.sub.t1, according to the following rules:
[0071] where l is the serial number of sampling value Y.sub.kl, Y.sub.(k1)(M.sub.
[0072] when in extraction mode, parallel reading out M.sub.t groups of sampling values from a FIFO memory in which the sampling values acquired by the data acquisition module are stored, where each group of sampling values has M.sub.ext sampling values, M.sub.ext is the extracting multiple; selecting a maximum value and a minimum value from each group of sampling values, where the maximum value and the minimum value are respectively represented by Y.sub.kl,max, Y.sub.kl,min, l is the serial number of group, l=0, 1, . . . , M.sub.t1, and then adjusting M.sub.t pairs of maximum values and minimum values Y.sub.kl,max, Y.sub.kl,min, l=0, 1, . . . , M.sub.t1, according to the following rules:
[0073] for maximum value Y.sub.k(l+1),max, l=0, 1, . . . , M.sub.t2, if Y.sub.k(l+1),max<Y.sub.kl,min, then letting Y.sub.k(l+1),max=Y.sub.kl,min, otherwise keeping it unchanged;
[0074] for maximum value Y.sub.k(l+1),min, l=0, 1, . . . , M.sub.t2, if Y.sub.k(l+1),min>Y.sub.kl,max, then letting Y.sub.k(l+1),min=Y.sub.kl,max, otherwise keeping it unchanged.
[0075] In one embodiment, the extracting multiple M.sub.ext is 16, groups of sampling values M.sub.t is 8.
[0076] Step S3.2.3: selecting a RAM R.sub.ih for each maximum value Y.sub.kl,max, a RAM R.sub.ig for each maximum value Y.sub.kl,min, l=0, 1, . . . , M.sub.t1, according to the following equations:
i=l, h=(2.sup.N1Y.sub.kl,max)/M.sub.a, g=(2.sup.N1Y.sub.kl,min)/M.sub.a
[0077] then selecting RAMs between RAM R.sub.ih and RAM R.sub.ig for each pairs of maximum values and minimum values Y.sub.kl,max, Y.sub.kl,min. The RAMs between RAM R.sub.ih and RAM R.sub.ig can be denoted by R.sub.if, f=(h+1), (h+1), . . . , (g1).
[0078] In one embodiment, i=l, h=(2.sup.81Y.sub.kl,max)/4, g=(2.sup.81Y.sub.kl,min)/4.
[0079] Step S3.2.4: calculating a physical address A.sub.kl,max for each maximum value Y.sub.kl,max and a physical address A.sub.kl,max for each maximum value Y.sub.kl,max, l=0, 1, . . . , M.sub.t1, according to the following equations:
[0080] In one embodiment,
[0081] Step S3.2.5: parallel updating the probability values of the storage units for the M.sub.t pairs of maximum values and minimum values: for each pair of maximum value and minimum value Y.sub.kl,max, Y.sub.kl,min, reading out probability values (initial values are 0) from storage units according to physical address scope [A.sub.kl,max, (2.sup.N/M.sub.a)(k+1)1] in RAM R.sub.ih, physical address scope [(2.sup.N/M.sub.a)k, A.sub.kl,min] in RAM R.sub.ig and physical address scope [(2.sup.N/M.sub.a)k, (2.sup.N/M.sub.a)(k+1)1] in each RAM between RAM R.sub.ih and RAM R.sub.ig, and adding 1 to each of the probability values, writing the added probability values back to their respective storage units.
[0082] In one embodiment, the physical address scope in RAM R.sub.ih is [A.sub.kl,max, (2.sup.8/4)(k+1)1], the physical address scope in RAM is R.sub.ig [(2.sup.8/4)k, A.sub.kl,min], the physical address scope in each RAM between RAM R.sub.ih and RAM R.sub.ig is [(2.sup.8/4)k, (2.sup.8/4)(k+1)1].
[0083] Step S3.2.6: setting serial number k of read to k+1, and returning to step S3.2.2, until L pairs of maximum values and minimum values have been mapped.
[0084] Step S3.2.7: returning to step S3.2.1, until a screen refresh signal arrives.
[0085] Step S4: reading out each probability value from each RAM, and reformulating it in term of percentage, then converting it into a luminance value H according to the following equations:
[0086] where P is the reformulated probability value, b, c are intermediate values, Lu is a luminance grade which is set by user.
[0087] In one embodiment, as shown in
[0088] While illustrative embodiments of the invention have been described above, it is, of course, understand that various modifications will be apparent to those of ordinary skill in the art. Such modifications are within the spirit and scope of the invention, which is limited and defined only by the appended claims.