Semiconductor device and method of manufacturing thereof

Abstract

A semiconductor device includes an n.sup.-type drift layer of an formed on an n.sup.+-type SiC substrate; a p-type layer provided on a surface opposite that facing the n.sup.+-type SiC substrate; and an n-type buffer layer provided, as a recombination promoting layer, between the n.sup.-type drift layer and the n.sup.+-type SiC substrate, the n-type buffer layer having an impurity concentration higher than that of the n.sup.-type drift layer. In the buffer layer, as a recombination site, a defect energy-level is introduced at a high concentration of 110.sup.12/cm.sup.3 or higher. The buffer layer promotes internal electron-hole recombination and without applying high energy to BPDs at an interface of the buffer layer and the SiC substrate, may reduce the amount of recombination near the interface even at a current density equivalent to that of a conventional structure and thereby, prevents characteristics degradation at the time of operation.

Claims

1. A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a high-resistance first semiconductor region of the first conductivity type, having a first surface and a second surface opposite to the first surface, and being formed on the semiconductor substrate, the second surface facing the semiconductor substrate; a second semiconductor region of a second conductivity type provided at the first surface of the high-resistance first semiconductor region; and a third semiconductor region of the first conductivity type provided between the high-resistance first semiconductor region and the semiconductor substrate, as a recombination promoting layer, the third semiconductor region having an impurity concentration higher than an impurity concentration of the high-resistance first semiconductor region, the third semiconductor region having defects each of which functions as a recombination site, a concentration of the defects in the third semiconductor region being higher than 110.sup.12/cm.sup.3, the third semiconductor region having a Z.sub.1/2 energy-level that is a carbon deficiency defect energy-level introduced by the defects.

2. A method of manufacturing a semiconductor device, comprising: forming a high-resistance first semiconductor region of the first conductivity type on a semiconductor substrate of the first conductivity type, the high-resistance first semiconductor region having an impurity concentration lower than an impurity concentration of the third semiconductor region; forming a second semiconductor region of a second conductivity type on the high-resistance first semiconductor region; and forming a third semiconductor region of the first conductivity type, the third semiconductor region being disposed between the high-resistance first semiconductor region and the semiconductor substrate, as a recombination promoting layer, the third semiconductor region having an impurity concentration higher than an impurity concentration of the high-resistance semiconductor region, the third semiconductor region having defects each of which functions as a recombination site, a concentration of the defects in the third semiconductor region being higher than 110.sup.12/cm.sup.3, the third semiconductor region having a Z.sub.1/2 energy-level that is a carbon deficiency defect energy-level introduced by the defects.

3. The method according to claim 2, further comprising: introducing a defect energy-level by carbon loss in entire area of each of the third semiconductor region and the high-resistance first semiconductor region, thereby introducing a carbon vacancy defect in the third semiconductor region and the high-resistance first semiconductor region; and reducing the carbon vacancy defects only at an upper region of the third semiconductor region with respect to the substrate.

4. The method according to claim 2, wherein said forming a third semiconductor region includes irradiating either an electron beam or protons on the third semiconductor region, thereby introducing the defect energy-level.

5. The method according to claim 3, further comprising performing carbon implantation on the second semiconductor region, wherein reducing the carbon vacancy defect includes annealing after the carbon implantation is performed.

6. The method according to claim 3, further comprising forming a carbon cap on the second semiconductor region, wherein reducing the carbon vacancy defect includes performing an oxidization after the carbon cap is formed.

7. The semiconductor device according to claim 1, wherein the third semiconductor region has the impurity concentration lower than an impurity concentration of the semiconductor substrate.

8. The semiconductor device according to claim 1, wherein the third semiconductor region includes equal to or more than 110.sup.18/cm.sup.3 of n-type impurities.

9. The method according to claim 2, wherein the third semiconductor region has the impurity concentration lower than an impurity concentration of the semiconductor substrate.

10. The method according to claim 2, wherein the third semiconductor region includes equal to or more than 110.sup.18/cm.sup.3 of n-type impurities.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a cross-sectional view of a structure of a semiconductor device according to an embodiment;

(2) FIG. 2 is a chart depicting forward operating voltage and density of holes reaching a substrate in the embodiment and in a conventional semiconductor device;

(3) FIG. 3 is a cross-sectional view of a structure of components in a conventional semiconductor device;

(4) FIG. 4 is a cross-sectional view of a structure of components in a conventional semiconductor device; and

(5) FIG. 5 is a cross-sectional view of a structure of components in a conventional semiconductor device.

BEST MODE(S) OF CARRYING OUT THE INVENTION

(6) Preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. In the description of the embodiments below and the accompanying drawings, main portions that are identical will be given the same reference numerals and will not be repeatedly described.

Embodiment

(7) A structure of the semiconductor device according to an embodiment will be described. FIG. 1 is a cross-sectional view of the structure of the semiconductor device according to the embodiment. A SiC PIN diode containing SiC in a semiconductor substrate will be described as an example of the semiconductor device. Description will be given using an example in which a first conductivity type is an n-type and a second conductivity type is a p-type.

(8) By epitaxial growth, a conversion layer 9 for BPD.fwdarw.TED conversion is formed on an n.sup.+-type SiC substrate 1 having a high concentration (e.g., 110.sup.19/cm.sup.3), and a buffer layer 6 of an n-type and promoting recombination is formed on the conversion layer 9.

(9) The buffer layer 6 has, for example, a concentration of 110.sup.18/cm.sup.3 or higher and a thickness of 1 m or greater. When the buffer layer 6 is formed, a C/Si ratio is adjusted so that an energy-level of a carbon vacancy defect is introduced, whereby the buffer layer 6 is formed as a buffer layer in which a defect energy-level has been introduced. A density of the introduced defect energy-level density is, for example, about 110.sup.12/cm.sup.3 or higher. The buffer layer 6 itself functions as a recombination promoting layer, however, due to the density of the defect energy-level at the predetermined high concentration described, the buffer layer 6 functions as a recombination site promoting recombination. As a recombination site, a Z.sub.1/2 energy-level that is a carbon deficiency defect energy-level may be used.

(10) On the buffer layer 6, a drift layer (high-resistance semiconductor region) 2 containing an n.sup.-type SiC at a concentration of, for example, about 110.sup.14/cm.sup.3 or higher is formed by epitaxial growth or the like. The drift layer 2 constitutes a breakdown voltage sustaining layer. While a concentration and thickness of the drift layer 2 varies according to the breakdown voltage, for example, for a 1200V element, the concentration is about 110.sup.15/cm.sup.3 or higher and the thickness is about 10 m or greater, and for a 20 kV element, the concentration is about 410.sup.14/cm.sup.3 or lower and the thickness is about 150 m or greater.

(11) Next, on the drift layer 2, a p-type-impurity epitaxial layer is formed or a p-type layer (second semiconductor region) 3 having a high concentration is formed by ion implantation, creating a PIN diode. A concentration of the p-type layer 3 may be 110.sup.16/cm.sup.3 or higher, which is sufficiently higher than the concentration of the drift layer 2 and a thickness of the p-type layer 3 may be about 0.1 to several m. When the concentration of the p-type layer 3 is not sufficiently higher than the impurity concentration of the drift layer 2 and the thickness of the p-type layer 3 is thin, breakdown voltage decreases due to punch-though to an upper electrode and therefore, caution is necessary.

(12) Subsequently, in a case where the p-type layer 3 is formed by epitaxial growth, an edge termination structure that mitigates electric field in a lateral direction of the p-type layer 3 is formed after a high-concentration p-type region is removed by etching a part of an outer periphery of the p-type layer 3 to form a low-concentration p-type region at a periphery. Subsequently, a front electrode 7 and a rear electrode 8 are each formed.

(13) In a structure of the PIN diode above, a high-concentration impurity layer (the buffer layer 6) is provided and has a much higher impurity concentration (e.g., about 110.sup.18/cm.sup.3 of higher) than the epitaxial layer (the drift layer 2) having a low impurity concentration and sustaining the breakdown voltage.

(14) A minority carrier density in the drift layer 2 may be kept high by a potential barrier due to the high impurity concentration of the buffer layer 6 and therefore, resistivity at the time of bipolar operation may be reduced. Normally, in a high voltage device, the drift layer 2 is thick and the carrier density is low. Therefore, when the minority carrier density in the drift layer 2 decreases, the resistivity at the time of bipolar operation increases. Thus, in the embodiment, in the drift layer 2, since no defect energy-level is introduced, increases in resistance do not occur.

(15) Compared to the drift layer 2, the buffer layer 6 has a high impurity concentration and many carriers and thus, has low resistance, and since the thickness is thin (e.g., about 1 m to 10 m), even when carriers in the buffer layer 6 decrease, increases in resistance at the time of bipolar operation are small. Therefore, even when hole-electron recombination is promoted and carriers decrease according to the defect energy-level, a low resistance at the time of bipolar operation may be maintained.

(16) In the buffer layer 6, electron-hole recombination by Auger recombination due to the high impurity concentration is promoted. Since recombination is further promoted via a deep defect energy-level introduced in the buffer layer 6, in the buffer layer 6, the minority carriers nearly disappear and recombination at the interface of the buffer layer 6 and the conversion layer 9, or in the n.sup.+-type SiC substrate 1 becomes very low and therefore, no high energy is applied to BPDs present near the interface. As a result, BPD expansion is suppressed and characteristics degradation may be prevented.

Second Embodiment

(17) The PIN diode of a second embodiment has substantially the same structure that is described in the first embodiment and that includes the buffer layer 6. In the second embodiment, on the n.sup.+-type SiC substrate 1 having a high concentration (e.g., 110.sup.19/cm.sup.3), during the epitaxial growth of the buffer layer 6 of an n-type and the drift layer 2, etc., in the drift layer 2 and the buffer layer 6 overall, the C/Si ratio is adjusted so that a defect energy-level is introduced due to carbon loss.

(18) Subsequently, before electrode (the front electrode 7 and the rear electrode 8) formation, carbon vacancy defects are reduced by annealing for a long period after carbon implantation or by oxidation for a long period after carbon capping; the carbon vacancy are reduced only at a region closer than the buffer layer 6, to a front surface. Other aspects are the same processes and structures as in the first embodiment.

Third Embodiment

(19) The PIN diode of a third embodiment has substantially the same structure that is described in the first embodiment and that includes the buffer layer 6. In the third embodiment, on the n.sup.+-type SiC substrate 1 having a high concentration (e.g., 110.sup.19/cm.sup.3), the conversion layer 9 for BPD.fwdarw.TED conversion is formed by epitaxial growth or the like. Then, on the conversion layer 9, the buffer layer 6 of an n-type and promoting recombination is formed by epitaxial growth or the like and has, for example, a concentration of 110.sup.18/cm.sup.3 or higher, and a thickness of 1 m or greater.

(20) After formation of the buffer layer 6, electron beam irradiation or proton irradiation is performed so as to introduce a defect energy-level in the buffer layer 6. The density of the introduced defect energy-level is, for example, about 110.sup.12/cm.sup.3 or higher. Other aspects are the same processes and structures as in the first embodiment.

(21) According to the embodiments, even with operation at a high current density, characteristics degradation such as increases in ON resistance due to defect expansion may be prevented. Further, compared to a case in which a defect energy-level is introduced in a semiconductor element overall, resistivity at the time of bipolar operation may be reduced. Furthermore, compared to a case where a defect energy-level is introduced in a semiconductor element overall, resistivity at the time of unipolar operation may be reduced. Introduction of a defect energy-level enables minority carriers to be inhibited from reaching the semiconductor substrate even with high current density, whereby the thickness of the high-concentration buffer may be reduced, achieving an effect in that device fabrication costs may be reduced.

(22) FIG. 2 is a chart depicting forward operating voltage and density of holes reaching the substrate in the embodiment and in a conventional semiconductor device. FIGS. 3 to 5 are cross-sectional views of a structure of components the conventional semiconductor devices. FIG. 3 depicts a structure without a buffer layer and having only a conversion layer 109. FIG. 4 depicts a structure having in a drift layer overall, an n.sup.-type drift layer 105 in which a defect energy-level of 110.sup.13/cm.sup.3 is introduced. FIG. 5 depicts a structure having a conversion layer 109 and a buffer layer 104.

(23) FIG. 2 depicts operating voltage values and density values of minority carriers (in this case, holes) reaching a vicinity of the n.sup.+-type SiC substrates 1, 101/the drift layers 2, 102 of the above four types of diodes (1) to (4) operating at a same current density (100 A/cm.sup.2) estimated by simulation. (1) 13 kV PIN diode without high-impurity-concentration buffer layer (conventional structure, FIG. 3) (2) PIN diode having the n.sup.-type drift layer 105 in which a defect energy-level of 110.sup.13/cm.sup.3 is introduced in the drift layer overall (conventional structure, FIG. 4) (3) PIN-type diode having the n-type buffer layer 104 of a high impurity concentration (510.sup.18/cm.sup.3) and a thickness of 5 m (conventional structure, FIG. 5) (4) PIN diode having the buffer layer 6 of a high impurity concentration that is the same as the defect energy-level of 110.sup.13/cm.sup.3 introduced only in the buffer layer (first embodiment, FIG. 1)

(24) As depicted in FIG. 2, use of the structure of the embodiment enables increases of the operating voltage to be suppressed to about 0.3V or less while the density of minority carriers (in this case, holes) near the n.sup.+-type SiC substrate 1/the drift layer 2 is reduced to 1/100 or less of that in the conventional structures (1), (3). Further, in the conventional structure (2) in which a defect energy-level is introduced overall, although minority carriers may be suppressed to an extent that minority carriers are substantially not present, operation becomes substantially unipolar operation and the operating voltage becomes 27V and therefor, conduction loss increases significantly.

(25) In the embodiments, although a PIN diode formed on an n-type SiC substrate has been described as an example, application to a similar device of different polarities (e.g., NIP diode on a p-type substrate) is similarly possible. Further, application is similarly possible to a built-in PN diode in a unipolar device such as a MOS. Application to an IGBT, a thyristor, etc. is further possible. Application to a semiconductor device, etc. that uses a substrate containing another wide bandgap material (GaN, gallium oxide, etc.) is also possible.

(26) In the embodiments, various modifications within a scope not departing from the spirit of the present invention are possible. In the embodiments, for example, dimensions, impurity concentration, etc. of regions may be variously set according to required specifications. Further, in the embodiments, although the first conductivity type is assumed to be an n-type and the second conductivity type is assumed to be a p-type, the present invention is similarly implemented when the first conductivity type is a p-type and the second conductivity type is an n-type.

INDUSTRIAL APPLICABILITY

(27) As described, the semiconductor device and the method of manufacturing the semiconductor device according to the embodiments of the present invention is useful for bipolar semiconductor devices having a high breakdown voltage.

EXPLANATIONS OF LETTERS OR NUMERALS

(28) 1 semiconductor substrate (n.sup.+-type SiC substrate) 2 n.sup.-type drift layer 3 p-type layer 4 n-type buffer layer 5 n.sup.-type drift layer in which defect energy-level is introduced 6 n-type buffer layer in which defect energy-level is introduced 7 front electrode 8 rear electrode 9 conversion layer