Fabrication method of semiconductor substrate

Abstract

A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; foil ling a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.

Claims

1. A method for fabricating a semiconductor substrate, comprising the steps of: forming a first dielectric layer on a substrate body; forming a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias, wherein when the second dielectric layer is formed, the second dielectric layer does not completely fill the first vias and at least one closed space is formed in the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.

2. The method of claim 1, wherein the etching step further comprises etching portions of the first dielectric layer so as for the openings to extend into the first dielectric layer.

3. The method of claim 1, wherein forming the circuit layer and the conductive vias comprises: forming a metal layer in the first vias and the openings and on a top surface of the second dielectric layer by electroplating; and removing the metal layer on the top surface of the second dielectric layer such that the metal layer in the openings constitutes the circuit layer and the metal layer in the second vias constitutes the conductive vias.

4. The method of claim 3, wherein the metal layer on the top surface of the second dielectric layer is removed by chemical mechanical polishing (CMP).

5. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are made of silicon oxide.

6. The method of claim 1, wherein the circuit layer and the conductive vias are made of copper.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic cross-sectional view of a conventional package structure having a silicon interposer;

(2) FIGS. 2A to 2I are schematic cross-sectional view showing a conventional self-aligned dual damascene process; and

(3) FIGS. 3A to 3I are schematic cross-sectional views showing a semiconductor substrate and a fabrication method thereof according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(4) The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.

(5) It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as first, second, a etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.

(6) FIGS. 3A to 3I are schematic cross-sectional views showing a semiconductor substrate and a fabrication method thereof according to the present invention.

(7) Referring to FIG. 3A, a first dielectric layer 31 is formed on a substrate body 30. The first dielectric layer 31 can be made of silicon oxide. The substrate body 30 can have circuits (not shown) formed thereon.

(8) Referring to FIG. 3B, a first resist layer 32 is formed on the first dielectric layer 31 and patterned to expose portions of the first dielectric layer 31.

(9) Referring to FIG. 3C, the exposed portions of the first dielectric layer 31 are removed by etching to form a plurality of first vias 310 penetrating the first dielectric layer 31 and exposing portions of the substrate body 30. Then, the first resist layer 32 is removed.

(10) Referring to FIG. 3D, a second dielectric layer 33 is formed on the first dielectric layer 31 and the exposed portions of the substrate body 30. The second dielectric layer 33 can be made of silicon oxide. The second dielectric layer 33 further extends on walls of the first vias 310. Preferably, the second dielectric layer 33 has a poor gap filling capability such that the second dielectric layer 33 does not completely fill the first vias 310 and spaces V are formed in the first vias 310.

(11) Referring to FIG. 3E, a second resist layer 34 is formed on the second dielectric layer 33 and patterned to expose portions of the second dielectric layer 33.

(12) Referring to FIG. 3F, the exposed portions of the second dielectric layer 33 and portions of the first dielectric layer 31 under the second dielectric layer 33 are removed by etching so as to form a plurality of openings 35 communicating with the first vias 310 and a plurality of second vias 330 penetrating the second dielectric layer 33 in the first vias 310 for exposing portions of the substrate body 30, and the second dielectric layer 33 on the walls of the first vias 310 is retained. Although the openings 35 extend into the first dielectric layer 31 in the present embodiment, the invention is not limited thereto.

(13) Referring to FIG. 3G the second resist layer 34 is removed.

(14) Referring to FIG. 3H, a metal layer 36 is formed in the first vias 310, the openings 35 and a top surface of the second dielectric layer 33. The metal layer 36 can be made of copper.

(15) Referring to FIG. 3I, the metal layer 36 on the top surface of the second dielectric layer 33 is removed by a chemical mechanical polishing (CMP) process. As such, the metal layer 36 in the openings 35 constitutes a circuit layer 362 and the metal layer 36 in the second vias 330 constitutes a plurality of conductive vias 361 for electrically connecting the circuit layer 362 and the substrate body 30.

(16) The present invention further provides a semiconductor substrate, which has: a substrate body 30; a first dielectric layer 31 formed on the substrate body 30 and having a plurality of first vias 310 exposing portions of the substrate body 30; a second dielectric layer 33 formed on the first dielectric layer 31 and in the first vias 310, wherein a plurality of openings 35 are formed in the second dielectric layer 33 and communicating with the first vias 310, and a plurality of second vias 330 are formed to penetrate the second dielectric layer 33 in the first vias 310 so as to expose portions of the substrate body 30, leaving the second dielectric layer 33 on walls of the first vias 310; a circuit layer 362 formed in the openings 35; and a plurality of conductive vias 361 formed in the second vias 330 for electrically connecting the circuit layer 362 and the substrate body 30.

(17) In the above-described semiconductor substrate, the openings 35 further extend into the first dielectric layer 31.

(18) In the above-described semiconductor substrate, the first dielectric layer 31 and the second dielectric layer 33 can be made of silicon oxide, and the circuit layer 362 and the conductive vias 361 can be made of copper.

(19) Therefore, the present invention dispenses with the etch stop layer so as to reduce the fabrication cost and prevent the capacitance effect induced by the etch stop layer and simplify the fabrication process. Further, since the second dielectric layer does not completely fill the first vias, the present invention can shorten the time to form the second vias via etching and reduce the critical diameters of the second vias and the conductive vias.

(20) The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.