LAMINATED ELECTRONIC COMPONENT AND MOUNTING STRUCTURE THEREOF

Abstract

A laminated electronic component includes a rectangular parallelepiped shaped stacked body including dielectric layers and internal electrode layers which are alternately laminated and a pair of first conductors and a pair of second conductors which are disposed on an outer surface of the stacked body. The first conductors are disposed in portions which include centers of long sides of a first principal surface which is positioned in a direction of lamination of the dielectric layers and the internal electrode layers of the stacked body, and do not include a vertex of the stacked body so as to extend from first side surfaces to the first principal surface. The second conductors are disposed on second side surfaces, and the first conductors and the second conductors are spaced apart from each other on an outer surface and electrically connected to each other via the internal electrode layers.

Claims

1. A laminated electronic component comprising: a stacked body having a rectangular parallelepiped shape, the stacked body comprising dielectric layers and internal electrode layers which are alternately laminated; and a pair of first conductors and a pair of second conductors disposed on an outer surface of the stacked body, the stacked body comprising a pair of first and second principal surfaces which has a rectangular shape and is positioned in a direction of lamination of the dielectric layers and the internal electrode layers, a pair of first side surfaces adjacent to long sides of the pair of first and second principal surfaces, and a pair of second side surfaces adjacent to short sides of the pair of first and second principal surfaces, the pair of first conductors being disposed in portions which include centers of the long sides of the first principal surface or the second principal surface, and do not include a vertex of the stacked body, and the pair of first conductors comprising side surface sections which extend from the long sides on the pair of first side surfaces, and projection sections which extend from the long sides or the short sides on the first principal surface, the pair of second conductors being disposed on the pair of first side surfaces or the pair of second side surfaces, and the pair of first conductors and the pair of second conductors being spaced apart from each other on the outer surface and electrically connected to each other via the internal electrode layers.

2. The laminated electronic component according to claim 1, wherein a length in the direction of lamination of each of the side surface sections of the pair of first conductors is equal to or less than 0.4 time a length in the direction of lamination of the stacked body.

3. The laminated electronic component according to claim 1, wherein the side surface sections of the pair of first conductors, and the pair of second conductors are respectively disposed on different side surfaces among the pair of first side surfaces and the pair of second side surfaces.

4. The laminated electronic component according to claim 3, wherein the side surface sections of the pair of first conductors are disposed on the pair of first side surfaces, and the pair of second conductors is disposed on the pair of second side surfaces.

5. The laminated electronic component according to claim 1, wherein the side surface sections of the pair of first conductors and the pair of second conductors are disposed on one of the pair of first side surfaces.

6. The laminated electronic component according to claim 1, wherein the pair of second conductors is disposed over an entirety in the direction of lamination of the pair of first side surfaces or the pair of second side surfaces.

7. A mounting structure, comprising: the laminated electronic component according to claim 1; and a substrate which is joined with the projection sections of the pair of first conductors of the laminated electronic component.

8. The laminated electronic component according to claim 1, wherein when a length of the long sides is denoted by L and a length of the pair of first conductors along the long sides is denoted by W, a ratio of W to L is equal to or less than 0.35.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0011] FIGS. 1A to 1C illustrate a laminated electronic component according to a first embodiment, in which FIG. 1A is a perspective view, FIG. 1B is a sectional view taken along the line A1-A1 of FIG. 1A, and FIG. 1C is a sectional view taken along the line A2-A2;

[0012] FIG. 2A is a sectional view taken along the line A3-A3 of FIG. 1A, FIG. 2B is a sectional view on a first principal surface side compared to FIG. 2A, and FIG. 2C is a plan view of FIG. 1A as viewed from the first principal surface side;

[0013] FIG. 3 is a sectional view taken along the line A1-A1 of FIG. 1A illustrating a mounting structure in which the laminated electronic component is mounted on a substrate according to the first embodiment;

[0014] FIG. 4 is a perspective view of a calculation result of a vibration mode of the laminated electronic component at 10 kHz as viewed from a symmetry plane side in the first embodiment;

[0015] FIGS. 5A and 5B illustrate another example of the first embodiment, in which FIG. 5A is a perspective view and FIG. 5B is a sectional view taken along the line B1-B1 of FIG. 5A;

[0016] FIGS. 6A and 6B illustrate a laminated electronic component according to a second embodiment, in which FIG. 6A is a perspective view and FIG. 6B is a plan view as viewed from the first principal surface side of FIG. 6A;

[0017] FIGS. 7A to 7C illustrate a laminated electronic component along a third embodiment, in which FIG. 7A is a perspective view, FIG. 7B is a plan view as viewed from the first principal surface side of FIG. 7A, and FIG. 7C is a sectional view of line C-C of FIG. 7A;

[0018] FIGS. 8A to 8C illustrate a laminated electronic component of the related art, in which FIG. 8A is a perspective view, FIG. 8B is a plan view as viewed from a z-axis direction of a coordinate axis, and FIG. 8C illustrates a mounting structure of the related art in which the laminated electronic component is mounted on a substrate, and is a sectional view of line D-D of FIG. 8B;

[0019] FIG. 9 is a schematic view of a measuring device of a sound pressure level;

[0020] FIGS. 10A and 10B illustrate a sound pressure level of a laminated ceramic capacitor in the mounting structure of the related art, in which FIG. 10A is a graph illustrating a measured sound pressure level and FIG. 10B is a graph illustrating a sound pressure level which is obtained by simulation;

[0021] FIG. 11 is a graph illustrating an impedance measurement result in a case where DC bias of 4V is applied to a laminated ceramic capacitor of the related art;

[0022] FIG. 12 is a schematic view of a model of a finite element method used for simulation of impedance of the laminated ceramic capacitor of the related art;

[0023] FIGS. 13A and 13B are perspective views illustrating a calculation result of a vibration mode of the laminated ceramic capacitor of the related art at 10 kHz, in which FIG. 13A is a view as viewed from a symmetry plane side and FIG. 13B is a view as viewed from a surface side; and

[0024] FIG. 14 is a perspective view schematically illustrating node-shaped sections of a vibration mode in the laminated ceramic capacitor of the related art.

DESCRIPTION OF EMBODIMENTS

[0025] A laminated electronic component and a mounting structure will be described with reference to the drawings. Moreover, in each drawing, the same reference numerals are given to the same members and portions and duplicate description will be omitted. Some of the reference numerals are omitted in some drawings. In addition, for ease of description, xyz coordinate axes are attached to each drawing.

First Embodiment

[0026] As illustrated in FIGS. 1A to 1C, a laminated electronic component 1 according to a first embodiment includes a rectangular parallelepiped-shaped stacked body 2, a pair of first conductors 3, and a pair of second conductors 4 disposed on an outer circumferential side surface. FIG. 1B is a sectional view taken along the line A1-A1 of FIG. 1A and as illustrated in FIG. 1B the stacked body 2, in which dielectric layers 5 and internal electrode layers 6 are alternately laminated in a z-axis direction of a coordinate axis, is provided. Moreover, a direction of lamination of the dielectric layers 5 and the internal electrode layers 6 may be simply referred to as the direction of lamination.

[0027] A first principal surface 7A and a second principal surface 7B which are a pair of opposed rectangular principal surfaces are positioned in the direction of lamination of the stacked body 2 in the laminated electronic component 1 of the embodiment. Both of the first principal surface 7A and the second principal surface 7B are configured of a pair of long sides 8 and a pair of short sides 9. The stacked body 2 has a pair of opposed first side surfaces 10 adjacent to the long sides 8 and a pair of opposed second side surfaces 11 adjacent to the short sides 9 of the first and second principal surfaces 7A and 7B

[0028] The first conductor 3 has a side surface section 3a disposed on the first side surface 10 and a projection section 3b extending from the side surface section 3a on the first principal surface 7A. The side surface section 3a is disposed closer to the first principal surface 7A than a center portion of the first side surface 10 in the direction of lamination. The second conductor 4 is disposed on the second side surface 11 and is spaced apart from the first conductor 3. That is, the first conductor 3 and the second conductor 4 are spaced apart from each other and are not connected to each other on the outer surface of the stacked body 2.

[0029] In the embodiment, as illustrated in FIGS. 2A and 2B, at least two types of the internal electrode layers 6 exist. That is, one is an internal electrode layer 6 including only lead-out sections 6b (FIG. 2A) and the other is an internal electrode layer 6 including lead-out sections 6a and the lead-out sections 6b (FIG. 2B).

[0030] As illustrated in FIG. 2A, the internal electrode layers 6 including only the lead-out sections 6b are further composed of an internal electrode layer 6 including the lead-out section 6b indicated by a solid line and an internal electrode layer 6 including the lead-out section 6b indicated by a broken line. As illustrated in FIG. 1C, the former and the latter internal electrode layers 6 are alternately laminated. The lead-out section 6b indicated by the solid line is exposed to the second side surface 11 which is positioned on a left side in FIG. 2A and the lead-out section 6b indicated by the broken line is exposed to the second side surface 11 which is positioned on a right side in FIG. 2A.

[0031] As illustrated in FIG. 2B, the internal electrode layers 6 including the lead-out sections 6a and the lead-out sections 6b are further composed of an internal electrode layer 6 including the lead-out sections 6a and 6b indicated by solid lines and an internal electrode layer 6 including the lead-out sections 6a and 6b indicated by broken lines. In FIG. 2B, the lead-out section 6a indicated by the solid line is exposed to the first side surface 10 which is positioned on a lower side and the lead-out section 6b indicated by the solid line is exposed to the second side surface 11 which is positioned on the left side. The lead-out section 6a indicated by the broken line is exposed to the first side surface 10 which is positioned on an upper side and the lead-out section 6b indicated by the broken line is exposed to the second side surface 11 which is positioned on the right side.

[0032] In FIGS. 2A and 2B, the internal electrode layers 6 including the lead-out sections 6b indicated by the solid lines are electrically connected to each other by the second conductor 4 on the left side and are further electrically connected to the side surface sections 3a of the first conductors 3 on the lower side by the lead-out sections 6a indicated by the solid lines. The internal electrode layers 6 including the lead-out sections 6b indicated by the broken lines are electrically connected to each other by the second conductor 4 on the right side and are further electrically connected to the side surface sections 3a of the first conductors 3 on the upper side by the lead-out sections 6a indicated by the broken lines.

[0033] As described above, the lead-out sections 6a are disposed so as to be alternately exposed to any one of the pair of first side surfaces 10 and are electrically connected to the side surface sections 3a of the first conductors 3. The lead-out sections 6b are disposed so as to be alternately exposed to any one of the pair of second side surfaces 11 and are electrically connected to the second conductors 4. The internal electrode layers 6 including the lead-out sections 6a and 6b are disposed such that conduction is not disposed between the first conductors 3 and between the second conductors 4. Moreover, in FIG. 1B, an example in which the lead-out section 6a of one layer of the internal electrode layers 6 is connected to each of the pair of first conductors 3, is illustrated, but the lead-out sections 6a of plural layer of the internal electrode layers 6 may be connected to each of the pair of first conductors 3.

[0034] The internal electrode layer 6 (FIG. 2B) including the lead-out sections 6a and 6b is positioned closer to the first principal surface 7A than the center portion in the direction of lamination in the first side surface 10 and the internal electrode layer 6 (FIG. 2A) including only the lead-out sections 6b configures the other internal electrode layers 6.

[0035] FIG. 2C is a plan view of the laminated electronic component 1 according to the embodiment as viewed from the first principal surface 7A side and illustrates dimensions of each portion. As illustrated in FIG. 2C, the first conductors 3 include center portions 8c of the long sides 8 and are positioned at portions which do not include vertexes V of the stacked body 2. Moreover, the center portion 8c of the long side 8 is a bisecting point bisecting a length of the long side 8.

[0036] Since an exposed section of the lead-out section 6a in the first side surface 10 is directivity connected to the first conductor 3, from the viewpoint that symmetry of vibration is maintained and factors causing vibration of the substrate can be reduced when being mounted, it is preferable that the center portions 8c of the long sides 8 are included.

[0037] Moreover, structures of the dielectric layers 5 and the internal electrode layers 6 illustrated in FIG. 1B are schematic, and actually, a laminated electronic component, in which the dielectric layers 5 and the internal electrode layers 6 of several layers to hundreds layers are laminated, is often used. This also applies to other embodiments described later.

[0038] The dimensions of each portion will be described with reference to FIG. 2C. In FIG. 2C, the length of the long side 8 is L1 and a length of the short side 9 is L2. W1 is a length of the first conductor 3 in a length direction (x-axis direction) of the long side 8 and P1 is a length of the projection section 3b in a direction (y-axis direction) perpendicular to the long side 8. From the viewpoint of reduction of the vibration of the substrate during being mounted on the substrate, it is preferable that a ratio (W1/L1) of W1 to L1 is equal to or less than 0.35 and, from the viewpoint of mounting reliability, is equal to or greater than 0.2.

[0039] The mounting structure of the laminated electronic component of the embodiment will be described. FIG. 3 is a sectional view illustrating a state where the laminated electronic component 1 is mounted on a substrate 12. In the mounting structure of the embodiment, as illustrated in FIG. 3, the projection sections 3b of the first conductors 3 of the laminated electronic component 1 and land patterns 13 on the substrate 12 are joined via a conductive material such as solder. Here, the laminated electronic component 1 and the substrate 12 are joined so as to be opposed with a predetermined gap between the first principal surface 7A and a mounting surface of the substrate 12. Conductive layers 14 such as solder applied on the land patterns 13 are formed between the first conductors 3 and the land patterns 13. As described above, in a case where the laminated electronic component 1 is mounted on the substrate 12 by applying the conductive material, the conductive material to be used is not particularly limited as long as the conductive material has good wettability with the first conductor 3.

[0040] In FIG. 3, H0 is a height of the laminated electronic component 1 in the direction of lamination (z-axis direction) of the stacked body 2, H1 is a length in the direction of lamination (z-axis direction) of the side surface section 3a of the first conductor 3 on the first side surface 10, and C is a gap between the mounting surface of the substrate 12 and the laminated electronic component 1.

[0041] On the other hand, as illustrated in FIG. 8A, the laminated electronic component of the related art includes a rectangular parallelepiped-shaped stacked body 102 and external electrodes 103 respectively disposed on outer surfaces of both end portions. FIG. 8B is a plan view as viewed from a z-axis direction of FIG. 8A and FIG. 8C is a sectional view illustrating a mounting structure of the related art.

[0042] As illustrated in FIG. 8C, the stacked body 102 comprises a stack in which dielectric layers 105 and internal electrode layers 106 are alternately laminated. The internal electrode layers 106 are electrically connected to the external electrodes 103 in one of both end surfaces of the stacked body 102.

[0043] For example, in a laminated ceramic capacitor which is one of the laminated electronic components, as the dielectric layer 105, a ferroelectric material such as barium titanate is used, and as the internal electrode layer 106, a metal material such as Ni is used. In addition, usually, the external electrode 103 is formed by baking Cu paste as a base electrode and applying Ni and Sn plating on a surface thereof.

[0044] In the laminated electronic component of the related art, as illustrated in FIG. 8C, the external electrodes 103 and land patterns 13 on a substrate 12 are fixed in a state of being electrically connected via solders 114. Gaps between the external electrodes 103 and the land patterns 13 are filled with the solders 114, and the solders 114 further covers the external electrodes 103 covering end surfaces, side surfaces, and a part of upper and lower surfaces of the stacked body 102.

[0045] When an AC voltage together with a DC voltage (DC bias) is applied to the laminated ceramic capacitor which is mounted in such a state, a piezoelectric property occurs in the dielectric layers 105 due to the electrostriction effect by the DC voltage and piezoelectric vibration occurs due to the AC voltage. Furthermore, the piezoelectric vibration of the laminated ceramic capacitor is transmitted to the substrate 12 via the solders 114, and the substrate 12 vibrates. When the substrate 12 resonates at a resonance frequency in an audible range, a vibration sound called acoustic noise occurs.

[0046] As an example, in a case of a mounting structure of the related art in which the laminated ceramic capacitor which is the laminated electronic component of the related art is mounted on the substrate 12, acoustic noise was measured. For the measurement, as the laminated ceramic capacitor, Type 1005 laminated ceramic capacitor (capacity 10 F, rated voltage 4V, hereinafter, referred to as an evaluation component) and as the substrate 12, a substrate formed of a FR material of 10040 mm and thickness of 0.8 mm were used. The laminated ceramic capacitor was mounted on a center of the substrate 12 using solder of SnAgCu (SAC) type. After mounting the evaluation component on the substrate 12, a mounting state was observed with a microscope, and it was confirmed that a fillet height of the solder 114 was 460 m and a gap C between the substrate 12 and the evaluation component was 45 m.

[0047] As illustrated in FIG. 9, the measurement was performed using a measuring device of a sound pressure level. A mounting substrate 21 (hereinafter, simply referred to as the mounting substrate) in which the evaluation component is mounted on the substrate 12 was installed within an anechoic box 22 (inner dimensions 600700 mm and height 600 mm) and acoustic noise was collected by a sound collecting microphone 23 installed at a position away 3 mm from the center of the substrate 12 in a direction perpendicular to the substrate 12. A sound pressure level of the collected sound was measured by an amplifier 24 and a FET analyzer 25 (DS2100 manufactured by Ono Sokki Co., Ltd.). An acoustic noise measurement result is illustrated in FIG. 10A when applying the DC voltage (DC bias) of 4 V and the AC voltage of 20 Hz to 20 kHz and 1 Vp-p to the laminated ceramic capacitor.

[0048] Moreover, in FIG. 10A, the sound pressure level is indicated by A characteristic sound pressure level (dBA) and 0 dBA corresponds to the lowest sound pressure level that a person hears as a sound. This is the sound pressure level weighted for each frequency so as to be close to hearing of a person and is described in a sound level meter (noise meter) standard (JISC 1509-1:2005).

[0049] Next, simulation of the piezoelectric vibration of the laminated ceramic capacitor was performed. First, in a state where the DC voltage (DC bias) of 4V is applied to the evaluation component, impedance is measured. A measurement result is illustrated in FIG. 11.

[0050] Simulation of the impedance was performed by using a model (dielectric material: barium titanate based material, internal electrode: Ni, external electrode: Cu, stacked body dimensions: 1100620620 m, and external electrode thickness 20 m) based on the evaluation component. For piezoelectric resistance peaks existing in a frequency region of 2 GHz or more, fitting of material parameters of the evaluation component was performed so as to match an actually measured value. FIG. 12 schematically illustrates a model of a finite element method using the simulation of the impedance. This is a model considering symmetry and two cross sections appearing on a front surface and a cross section on a lower side of FIG. 12 are symmetrical surfaces.

[0051] The parameters (elastic stiffness c.sub.ij and piezoelectric constant e.sub.ij) of the dielectric layer 105 obtained by fitting are indicated in Table 1. From Table 1, it can be seen that there is anisotropy (c.sub.11>c.sub.33 and c.sub.22>c.sub.33) in the material characteristic of the dielectric layer 105 of the evaluation component. This may be caused by a compression stress by the internal electrode layers 106.

TABLE-US-00001 TABLE 1 Elastic Stiffness and Piezoelectric Constant of Dielectric Layer c.sub.11.sup.E 281.5 10.sup.9 N/m.sup.2 c.sub.12.sup.E 117.2 10.sup.9 N/m.sup.2 c.sub.13.sup.E 57.2 10.sup.9 N/m.sup.2 c.sub.22.sup.E 230.8 10.sup.9 N/m.sup.2 c.sub.23.sup.E 57.2 10.sup.9 N/m.sup.2 c.sub.33.sup.E 104.3 10.sup.9 N/m.sup.2 c.sub.44.sup.E 30.9 10.sup.9 N/m.sup.2 c.sub.55.sup.E 30.9 10.sup.9 N/m.sup.2 c.sub.66.sup.E 68.9 10.sup.9 N/m.sup.2 e.sub.31 22.2 C/m.sup.2 e.sub.32 27.8 C/m.sup.2 e.sub.33 4.75 C/m.sup.2 e.sub.15 2.94 C/m.sup.2 e.sub.24 2.94 C/m.sup.2

[0052] A model of the mounting structure was created and simulation was performed based on the parameters of the obtained dielectric layer 105 and the mounting substrate 21 (fillet height 460 m and a gap between the substrate and the evaluation component 45 m) which is used in the measurement. FIG. 10B is a graph illustrating a result which is obtained by converting a vibration amplitude of the mounting substrate 21 obtained by simulation into the A characteristic sound pressure level. The frequency characteristic of acoustic noise depends on the vibration characteristic of the evaluation component and the resonant mode of the mounting substrate 21. Therefore, results of the simulation illustrated in FIG. 10B are in good agreement with the actual measured value illustrated in FIG. 10A in the sound pressure level and the frequency characteristic particularly in a high sound pressure and a low frequency region of 10 kHz or less. Therefore, it is possible to confirm the influence on acoustic noise when changing the mounting structure or a structure of the evaluation component itself by performing the simulation using the parameters.

[0053] In addition, a vibration mode was calculated in the audible frequency region (20 Hz to 20 kHz) of the evaluation component using the obtained parameters. The model was used in the calculation. A calculation result in 10 kHz is illustrated in FIGS. 13A and 13B. Moreover, FIG. 13A is a view as viewed from an inner side (symmetry plane side) of the model and FIG. 13B is a view as viewed on a side opposite to FIG. 13A, that is, from an outside (surface side) of the model. Here, a broken line indicates a shape of the evaluation component of a state where the AC voltage is not applied and a solid line indicates a shape of the evaluation component in a state of maximum displacement by the AC voltage. From the results, it can be seen that the evaluation component in the audible frequency region performs expanding vibration in the direction of laminated surface and performs stretching vibration in a thickness direction (direction of lamination). From the results, as illustrated in FIG. 14 schematically indicating the entire evaluation component, it can be seen that regions in which the vibration amplitude is small, that is, regions 15 (hereinafter, node-shaped sections) which can be regarded as nodes of vibration exist in the center portion of each side in two principal surfaces positioned in the direction of lamination of the evaluation component. The node-shaped sections 15 also exist in the laminated electronic component 1 of the embodiment as in the evaluation component. Therefore, it is thought that when fixing the laminated electronic component 1 to the substrate 12 via the first conductors 3 and the conductive layers 14 such as solder, the laminated electronic component 1 is fixed in the node-shaped sections 15 and thereby propagation of the piezoelectric vibration of the laminated electronic component 1 to the substrate 12 is suppressed, and acoustic noise can be reduced.

[0054] In the embodiment, it is possible to fix the node-shaped sections 15 of the stacked body to the substrate 12 via the first conductors 3 by providing the first conductors 3 on the node-shaped sections 15 existing in the laminated electronic component 1.

[0055] Even if the lead-out sections 6a exist only in a part of the direction of lamination, that is, in the vicinity of the first principal surface 7A, simulation of acoustic noise was performed using the following model of the embodiment to confirm that the node-shaped sections 15 of the vibration exist and an effect is achieved on reduction of acoustic noise by the embodiment. External dimensions of the stacked body 2 are the same as those of the evaluation component and the internal electrode layers 6 having the lead-out sections 6a are disposed in a range of 90 m the first principal surface 7A in the direction of lamination. As illustrated in FIG. 2B, the lead-out sections 6a are exposed at a width 260 m in the vicinity of the center portions 8c of the long sides 8 in the first side surfaces 10 and are electrically connected to the first conductors 3. As illustrated in FIGS. 2C and 3, in the first conductor 3, W1 was 280 m, H1 was 100 m, and P1 was 80 m. In addition, in the mounting structure of the embodiment, C was 70 m. Other conditions regarding the laminated electronic component 1 were the same as those of the simulation of acoustic noise in the evaluation component described above.

[0056] FIG. 4 illustrates a vibration mode of the laminated electronic component 1 of the embodiment in 10 kHz. Moreover, in the calculation of the vibration mode, a model was used in consideration of the symmetry of the laminated electronic component 1 of the embodiment. FIG. 4 illustrates the model as viewed from the symmetry plane side. Here, a broken line indicates a shape of the laminated electronic component 1 of a state where the AC voltage is not applied and a solid line indicates a shape of the laminated electronic component 1 in a state where the laminated electronic component 1 is displaced to the maximum level by the AC voltage. It can be confirmed that the node-shaped sections 15 of the vibration exist in the center portion of the long side 8 and the short side 9 constituting the principal surface 7. Moreover, in the simulation of the vibration mode of the embodiment, a model in which P1 of the first conductor 3 is 0 m was used.

[0057] If results obtained by the simulation of the sound pressure in the embodiment are averaged over a frequency region of 5 Hz to 20 kHz, an average value of the sound pressure level was reduced by 19 dBa with respect to the mounting structure of the related art.

[0058] Moreover, in the embodiment, in the simulation described above, a ratio (W1/L1) of W1 (280 m) to L1 (1100 m) was set to 0.25, but even if the ratio is set to 0.35, the sound pressure level can be reduced by approximately 10 dBA with respect to that of the related art. In addition, it is preferable that W1/L1 is equal to or greater than 0.2 from the viewpoint of mountability.

[0059] Moreover, in the mounting structure of the embodiment, the laminated electronic component 1 does not directivity come into contact with the mounting surface of the substrate 12. Particularly, a ratio (C/H0) of C that is the gap between the laminated electronic component 1 and the mounting surface of the substrate 12 to H0 is equal to or greater than 0.05, particularly, is equal to or greater than 0.1.

[0060] Furthermore, according to the results of the vibration mode analysis of the evaluation component described above and the embodiment, since the vibration amplitude is large in the vicinity of the center of each surface constituting the stacked body 2, it is preferable that a ratio (H1/H0) of H1 to H0 is equal to or less than 0.4. In addition, since the vibration amplitude is large in the vicinity of the center even in the principal surface 7, a length P1 of the first conductor 3 in a direction perpendicular to the long side 8 is equal to or less than 0.25 as a ratio (P1/L2) to L2.

[0061] As described above, in the embodiment, the laminated electronic component 1 is fixed to the substrate 12 by the first conductors 3. Therefore, the first conductors 3 are disposed in the node-shaped sections 15 of the laminated electronic component 1, that is, in portions which include the center portions 8c of the long sides 8 of the first principal surface 7A and do not include the vertexes V of the stacked body 2, and thereby acoustic noise can be suppressed. On the other hand, the second conductors 4 are responsible for electrical connection between the internal electrode layers 6 and do not contribute to fixation with the substrate 12. Therefore, the second conductors 4 do not come into contact with the substrate 12, may be disposed in positions spaced apart from the first conductors 3 on the outer surface of the stacked body 2, and may be disposed so as to include the centers of the first and second side surfaces 10 and 11 and the vertexes V of the stacked body 2.

[0062] As illustrated in FIGS. 1A to 1C, for example, the second conductors 4 may be substantially disposed over the entire surface of the second side surfaces 11 (side surfaces on which the side surface sections 3a of the first conductors 3 are not provided) or may be disposed on the second side surfaces 11 only in a part in a direction (y-axis direction) of the short side and over an entirety in the direction of lamination (z-axis direction) (across from the short side 9 of the first principal surface 7A to the short side 9 of the second principal surface 7B). It may be disposed so as to include the short side 9 of the second principal surface 7B and not to include the short side 9 of the first principal surface 7A.

[0063] Moreover, in the embodiment, the first conductors 3 may be disposed not only on portions of the first principal surface 7A side but also on the same portions of the second principal surface 7B side as illustrated in FIGS. 5A and 5B. It is preferable that dispositions of the first conductors 3 disposed on the second principal surface 7B side are symmetrical with those on the first principal surface 7A side in the vertical direction. Therefore, all the first conductors 3 disposed on the first and second principal surface 7A and 7B sides can be used as electrodes for the substrate connection and facilitate mounting.

Second Embodiment

[0064] In a second embodiment, as illustrated in FIGS. 6A and 6B, first conductors 3 are disposed so as to include center portions 9c of short sides 9 and have side surface sections 3a extending on second side surfaces 11. Second conductors 4 are disposed on first side surfaces 10. In the first embodiment, an example in which the second conductors 4 are disposed substantially over the entire surfaces of the second side surfaces 11 in which the first conductors 3 are not provided, is illustrated, but as in the second embodiment, the second conductors 4 may be provided only in a part of the first side surfaces 10 in which the first conductors 3 are not provided. In addition, the second conductors 4 is only required to be spaced apart from the first conductors 3 on an outer surface of a stacked body 2 and a part thereof may go around to first and second principal surfaces 7A and 7B, or the side surfaces in which side surface sections 3a of the first conductors 3 are provided.

Third Embodiment

[0065] In a third embodiment, as illustrated in FIGS. 7A to 7C, first conductors 3 are provided so as to include center portions 8c of long sides 8 and have side surface sections 3a extending on first side surfaces 10. In the embodiment, two pairs of second conductors 4 are disposed on the first side surfaces 10 similar to the first conductors 3. In the embodiment, internal electrode layers 6 including lead-out sections 6a and 6b indicated on a right side of FIG. 7C are positioned on a first principal surface 7A side of a center portion in the direction of lamination.

[0066] As described above, the second conductors 4 is only required to be spaced apart from the first conductors 3 in the first side surfaces 10, may be disposed on the same side surfaces as the side surface sections 3a of the first conductors 3, or may be disposed on a boundary between the first side surface 10 and the second side surface 11. In addition, the second conductors 4 may be not only one pair but also two or more pairs.

[0067] In addition, the internal electrode layer 6 including only the lead-out section 6a may be provided. That is, the internal electrode layer 6 including only the lead-out section 6a may be disposed closest to the first principal surface 7A of the stacked body 2, the internal electrode layers 6 including the lead-out section 6a and the lead-out section 6b, and the internal electrode layers 6 including only the lead-out sections 6b may be sequentially disposed and thereby the second conductors 4 may be disposed spaced apart from the long side 8 or the short side 9.

[0068] In each embodiment described above, the shape and the disposition of the internal electrode layers 6 may be appropriately changed according to the disposition of the first conductors 3 and the second conductors 4.

[0069] Moreover, in each embodiment described above, for the first conductors 3 and the second conductors 4, the shapes thereof are mainly formed in rectangular shapes and preferable ranges of the dimensions and ratios are described, but the shapes of the first conductor 3 and the second conductor 4 are not limited to the rectangular shape, and other various shapes and irregular shapes are acceptable. In addition, various changes and modifications can be made without departing from the scope of the invention based on the description regarding the vibration modes and the node-shaped sections 15 of the laminated electronic component 1 confirmed by the simulation described above.

[0070] The invention is particularly suitably used in a case where, for example, a laminated ceramic capacitor, which uses a ferroelectric material such as barium titanate based material for the dielectric layer 5 and uses a metal material such as Ni, Cu, Ag, and AgPd for the internal electrode layer 6, is the laminated electronic component 1. Also in other laminated electronic components 1, it is applicable to a case where it is necessary to suppress excitation of the substrate 12 on which the laminated electronic component 1 is mounted and the like due to the piezoelectric vibration of the laminated electronic component 1 itself. The invention can exert a remarkable effect particularly in the laminated electronic component 1 of a model of Type 1005 or larger (external dimensions of Type 1005 or larger).

[0071] The invention is applicable to various existing laminated electronic components 1. In addition, there is also an advantage that a special jig is not required for mounting on the substrate 12.

[0072] Moreover, in the embodiment, although the laminated ceramic capacitor having a general shape is described as an example of the laminated electronic component 1, in addition, it is applicable to a laminated electronic component 1 of a thin type or having various structures.

[0073] Furthermore, as the first conductor 3 and the second conductor 4, for example, a material which is obtained by plating Ni and Sn on a base electrode made of Cu which is often used as the external electrode of the laminated ceramic capacitor, may be employed, but the first conductor 3 and the second conductor 4 which are composed only of a plating electrode without using the base electrode, can be suitably used. Since the base electrode composed of Cu is relatively soft, the piezoelectric vibration of the stacked body 2 is absorbed and attenuated to some extent, but in a case of only the plating electrode, the piezoelectric vibration of the stacked body 2 is not attenuated by the first conductor 3 and acoustic noise is remarkable. Therefore, it is possible to obtain a larger acoustic noise suppression effect by applying the invention.

REFERENCE SIGNS LIST

[0074] 1: Laminated electronic component

[0075] 2, 102: Stacked body

[0076] 3: First conductor

[0077] 103: External electrode

[0078] 4: Second conductor

[0079] 5, 105: Dielectric layer

[0080] 6, 106: Internal electrode layer

[0081] 7A: First principal surface

[0082] 7B: Second principal surface

[0083] 8: Long side

[0084] 8c: Center of long side

[0085] 9: Short side

[0086] 9c: Center of short side

[0087] 10: First side surface

[0088] 11: Second side surface

[0089] 12: Substrate

[0090] 13: Land pattern

[0091] 14, 114: Solder

[0092] 15: Node-shaped section

[0093] 21: Mounting substrate

[0094] 22: Anechoic box

[0095] 23: Sound collecting microphone

[0096] 24: Amplifier

[0097] 25: FET analyzer