Thin film transistor, array substrate, manufacturing method and display device

Abstract

A thin film transistor, an array substrate, a manufacturing method and a display device are provided. The thin film transistor includes a substrate and a gate layer, a source layer and a drain layer disposed on the substrate. The source layer and the drain layer are disposed in different layers and the drain layer and the gate layer are disposed in same and one layer.

Claims

1. An array substrate, comprising: a substrate; and a gate electrode, a source electrode and a drain electrode disposed on the substrate, wherein the source electrode and the drain electrode are disposed different layers, and the drain electrode and the gate electrode are disposed in same and one layer; the drain electrode and the gate electrode have a gap or a trench therebetween; the source electrode is disposed over the gate electrode, a gate insulating layer and a composite layer are disposed between the source electrode and the gate electrode, the gate insulating layer is disposed on the gate electrode and under the composite layer, the composite layer extends over the gate insulating layer and a part of the drain electrode and overlays the gap or trench; the array substrate further comprises a passivation layer and a pixel electrode, the passivation layer is disposed on the source electrode and the drain electrode, and provided with a via at a region corresponding to the drain electrode, the pixel electrode is disposed on the passivation layer, and the drain electrode is connected with the pixel electrode through the via; a projection of the source electrode on the substrate is overlapped with a projection of the gate electrode on the substrate.

2. The array substrate of claim 1, wherein the composite layer comprises an active layer and an ohmic contact layer disposed on the active layer, the active layer is formed of a non-crystalline silicon material and has a thickness ranging from 200 3000 , the ohmic contact layer is formed of a non-crystalline silicon material doped with phosphor element and has a thickness ranging from 200 3000 .

3. The array substrate of claim 1, wherein the composite layer comprises an active layer and an etching stop layer disposed on the active layer, the active layer is formed of at least one material of indium gallium zinc oxide, indium zinc oxide, indium tin oxide or indium gallium tin oxide, and the active layer has a thickness ranging from 100 2000 ; the etching stop layer is formed of at least two materials of silicon oxide, silicon nitride, hafnium oxide, or aluminum oxide, and has a thickness ranging from 500 4000 .

4. The array substrate of claim 1, wherein the gate insulating layer is a single, double or multiple layers and is formed of at least one material of silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride or aluminum oxide, and has a thickness ranging from 2000 6000 .

5. A method of manufacturing the array substrate according to claim 1, comprising: forming patterns of the gate electrode and the drain electrode on the substrate, the gate electrode and the drain electrode having a gap or a trench therebetween; forming a pattern of the gate insulating layer on the gate electrode; forming a pattern of the composite layer on the gate insulating layer and a part of the drain electrode; forming a pattern of a source electrode on the composite layer at a region corresponding to the gate electrode; forming a pattern of the passivation layer on the source electrode, a part of the composite layer not covered by the source electrode and a part of the drain electrode not covered by the composite layer; forming the via in the passivation layer, and forming a pattern of the pixel electrode on the passivation layer, the drain electrode and the pixel electrode being connected with each other through the via.

6. The method of claim 5, wherein the step of forming patterns of the a gate electrode and the drain electrode on the substrate, the gate electrode and the drain electrode having a gap or a trench therebetween comprises: forming an electrode metal film on the substrate and forming patterns of the gate electrode and the drain electrode by one patterning process.

7. The method of claim 6, wherein the step of forming the pattern of the gate insulating layer on the gate electrode comprises: forming a gate insulating layer film, and forming a pattern of the gate insulating layer on the gate electrode by one patterning process.

8. The method of claim 7, wherein the step of forming a pattern of the composite layer on the gate insulating layer and a part of the drain electrode comprises: forming a composite layer film, the composite layer film comprising an active layer film and an ohmic contact layer film disposed on the active layer, and forming a pattern of the composite layer on the gate insulating layer and a part of the drain electrode by one patterning process.

9. The method of claim 7, wherein the step of forming a pattern of the composite layer on the gate insulating layer and a part of the drain electrode comprises: forming a composite layer film, the composite layer film comprising an active layer film and an etching stop layer film disposed on the active layer, and forming a pattern of the composite layer on the gate insulating layer and a part of the drain electrode by one patterning process.

10. The method of claim 9, wherein the step of forming a pattern of the source electrode on the composite layer at a region corresponding to the gate electrode comprises: forming an electrode metal film, and forming a pattern of the source electrode on the composite layer at a region corresponding to the gate electrode by one patterning process.

11. The method of claim 8, wherein the step of forming a pattern of the source electrode on the composite layer at a region corresponding to the gate electrode comprises: forming an electrode metal film, and forming a pattern of the source electrode on the composite layer at a region corresponding to the gate electrode by one patterning process.

12. The array substrate of claim 1, wherein the gate electrode, the source electrode and the drain electrode are all formed of at least one material of molybdenum, molybdenum niobium alloy, titanium or copper, and the gate electrode, the source electrode and the drain electrode have thicknesses ranging from 2000 10000 .

13. The array substrate of claim 1, wherein the source electrode is in direct contact with the composite layer; the drain electrode is in direct contact with the composite layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to clearly illustrate the technical solution of the embodiments of the invention, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the invention and thus are not limitative of the invention.

(2) FIG. 1A is a schematically sectional view of a known thin film transistor;

(3) FIG. 1B is a schematically sectional view of a known array substrate;

(4) FIG. 2 is a schematically sectional view of an array substrate in Embodiment 1 of the present invention;

(5) FIGS. 3A and 3a are schematically sectional view and plan view of an array substrate formed with a gate layer and a drain layer respectively;

(6) FIGS. 3B and 3b are schematically sectional view and plan view of an array substrate formed with a gate insulating layer respectively;

(7) FIG. 3C-3E are schematically sectional views of an array substrate formed with a source layer;

(8) FIG. 3e is a plan view of an array substrate formed with a source layer;

(9) FIGS. 3F and 3f are schematically sectional view and plan view of an array substrate formed with a composite layer respectively;

(10) FIGS. 3G and 3g are schematically sectional view and plan view of an array substrate formed with a passivation layer and a via respectively;

(11) FIGS. 3H and 3h are schematically sectional view and plan view of an array substrate formed with a pixel electrode layer respectively;

(12) FIG. 4 is a plan view of an array substrate formed with a plurality of TFT arranged as an array.

REFERENCE NUMERALS

(13) P1,1substrate; P2,2gate layer; P3,3drain layer; P4,4gate insulating layer; P5,5composite layer; 50composite layer film; P6,6source layer; 60electrode metal film; P7,7passivation layer; P8,8pixel electrode layer; P9,9via; 21gate scan line; 61data line.

DETAILED DESCRIPTION

(14) In order to make objects, technical details and advantages of the embodiments of the invention apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the invention. Apparently, the described embodiments are just a part but not all of the embodiments of the invention. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the invention.

Embodiment 1

(15) The present embodiment provides a thin film transistor comprising:

(16) a substrate; and

(17) a gate layer, a source layer and a drain layer which are disposed on the substrate, the source layer and the drain layer being disposed in different layers, and the drain layer and the gate layer are disposed in same layer.

(18) The present embodiment further provides an array substrate comprising the above-mentioned thin film transistor.

(19) As illustrated in FIG. 2, in the thin film transistor, the drain layer 3 and the gate layer 2 are disposed on the substrate 1 and in the same layer, the drain layer 3 and the gate layer 2 are provided with a gap or a trench therebetween. The source layer 6 is disposed over the gate layer 2. A gate insulating layer 4 and a composite layer 5 are disposed between the source layer 6 and the gate layer 2. The gate insulating layer 4 is disposed on the gate layer 2 and under the composite layer 5. The composite layer 5 extends over the gate insulating layer 4 and a part of the drain layer 3, and overlays the gap or trench.

(20) The gate layer 2, the source layer 6 and the drain layer 3 may all be made of at least one material of molybdenum, molybdenum niobium alloy, aluminum, aluminum neodymium alloy, titanium or copper, and the gate layer 2, the source layer 6 and the drain layer 3 have thickness ranging from 2000 10000 .

(21) In this embodiment, the composite layer 5 comprises an active layer and an etching stop layer disposed on the active layer. The active layer is made of at least one material of indium gallium zinc oxide, indium zinc oxide, indium tin oxide or indium gallium tin oxide, and the active layer has a thickness ranging from 100 2000 ; the etching stop layer may be formed of at least two materials of silicon oxide, silicon nitride, hafnium oxide, or aluminum oxide, and has a thickness ranging from 500 4000 .

(22) The gate insulating layer 4 may be a single, double or multiple layers and may be formed of at least one material of silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride, or aluminum oxide, and has a thickness ranging from 2000 6000 .

(23) The array substrate in the present embodiment comprises the above-mentioned TFTs and further comprises a passivation layer 7 and a pixel electrode layer 8. The passivation layer 7 is disposed on the source layer 6 and the drain layer 3, and provided with a via 9 at a region corresponding to the drain layer 3. The passivation layer 7 may be formed of at least two materials of silicon oxide, silicon nitride, hafnium oxide or aluminum oxide and has a thickness ranging from 1000 4000 .

(24) The pixel electrode layer 8 is disposed on the passivation layer 7, the drain layer 3 is connected with the pixel electrode layer 8 through the via 9. The pixel electrode layer 8 may be formed of at least one material of indium gallium zinc oxide, indium zinc oxide, indium tin oxide or indium gallium tin oxide, and has a thickness ranging from 300 1500 .

(25) Accordingly, a method of the above-mentioned thin film transistor comprises a step of forming the gate layer 2 and the drain layer 3 in the same and one layer. Besides that, the manufacturing method further comprises a step of forming the passivation layer 7 and the via 9, and connecting the drain layer 3 and the pixel electrode layer 8 through the via 9.

(26) In one example, the manufacturing method of thin film transistor comprises a step of forming patterns on the substrate 1 through two patterning process, wherein the patterns comprise the gate layer 2, the drain layer 3 and the source layer 6. One of the two patterning process is used to form a pattern comprising the gate layer 2 and the drain layer 3 at the same time, and the another patterning process is used to form a pattern comprising the source layer 6.

(27) In the present invention, the patterning process may comprise only a photolithographic process, or comprise photolithographic process and etching process, moreover, it may further comprise other processes for forming predetermined patterns, such as printing, ink jet and the like. The photolithographic process refers to the process for forming patterns, which comprises film formation, exposure, development and the other processes, and adopts photoresist, mask, and exposure machine. Specific patterning process may be selected depending on the structure to be formed in the present invention.

(28) As illustrated in FIGS. 3A-3h, the above-mentioned manufacturing method of array substrate comprises for example the following steps (wherein steps S1)-S5) are those for forming the thin film transistor):

(29) Step S1): forming a pattern comprising a gate layer 2 and a drain layer 3 on the substrate 1 with a gap or trench between the gate layer 2 and the drain layer 3.

(30) In this step, an electrode metal film is first formed on the substrate 1, and then forming a pattern comprising a gate layer 2, a gate scan line 21 and a drain layer 3 by one patterning process using a mask, as illustrated in FIGS. 3A, and 3a. Here, the electrode metal film may be formed on the substrate 1 by deposition, sputtering or thermal evaporation.

(31) Here, in order to clearly illustrate the sectional structure of the array substrate in the present embodiment during a manufacturing process more prominently, the scales of sectional views 3A and plan view 3a are set to be different. At the same time, to facilitate understanding positional relationship between respective layers in the thin film transistor, layers in the plan views are set to be transparent to a certain degree. The following plan views and sectional views are shown in a same way.

(32) Step S2): forming a pattern comprising a gate insulating layer 4 on the gate layer 2.

(33) In this step, a gate insulating layer film is formed on the substrate 1 with completion of step S1), that is, a gate insulating layer 4 is formed on the gate layer 2, as illustrated in FIGS. 3B and 3b. The gate insulating layer film may be formed by plasma enhanced chemical vapor deposition, and the gate insulating layer 4 may be formed by one photolithographic process using a mask.

(34) Step S3): forming a pattern comprising the composite layer 5 on the gate insulating layer 4 and a part of the drain layer 3.

(35) In this step, a composite layer film 50 is formed on the substrate 1 with completion of step S2). The composite layer film may be formed by deposition, sputtering or thermal evaporation. As illustrated in FIG. 3C, the composite layer film 50 comprises an active layer film and an etching stop layer film disposed on the active layer film (the two layer films are deposited respectively during the preparation process). A pattern comprising the composite layer 5 is formed on the gate insulating layer 4 and the part of the drain layer 3 by one patterning process using a mask, as illustrated in FIGS. 3F and 3f. Of course, it is also possible to use other masks that can realize this structure, for example, a halftone mask.

(36) Step S4): forming a pattern comprising the source layer 6 on the composite layer 5 at a region corresponding to the gate layer 2.

(37) In this step, an electrode metal film 60 is formed on the substrate 1 with completion of step S3). As illustrated in FIG. 3D, a pattern comprising the source layer 6 and a data line 61 is formed on the composite layer 5 at regions corresponding to the gate layer 2 by one patterning process using a mask, as illustrated in FIGS. 3E and 3e. Here, the electrode metal film is formed on the substrate by deposition, sputtering or thermal evaporation. Of course, other masks that can realize this structure may also be used.

(38) It is understood that in order to simplify the process flow, in steps S3) and S4), it is possible to form the composite layer film 50 first (as illustrated in FIG. 3C), and then form the electrode metal film 60 (as illustrated in FIG. 3D); next, an upper layer pattern comprising a source layer 6 and a data line 61 is formed by patterning process (as illustrated in FIGS. 3E and 3e), and then a lower layer pattern comprising the composite layer 5 is formed by patterning process. Specific steps will not be described in detail here.

(39) So far, the thin film transistor is finished. The gate scan line 21 and the data line 61 are formed in advance, which facilitates wiring of the array substrate.

(40) Step S5): forming patterns comprising the passivation layer 7 and the via 9 on the source layer 6, the part of the composite layer 5 not covered by the source layer 6 as well as the part of the drain layer 3 not covered by the composite layer 5.

(41) In this step, the passivation layer film (PVX) is formed on the substrate 1 with completion of step S4), and then a pattern comprising the passivation layer 7 is formed on the source layer 6, the part of the composite layer 5 not covered by the source layer 6 and the part of the drain layer not covered by the composite layer 5 by one patterning process using a mask, and then a pattern comprising the via 9 is formed in the passivation layer 7 by etching (FIGS. 3g and 3G). Here, the passivation layer film is formed by deposition, sputtering or thermal evaporation. Of course, other masks that can realize this structure may be used.

(42) Step S6): forming a pattern comprising the pixel electrode layer 8 on the passivation layer 7, the drain layer 3 and the pixel electrode layer 8 being connected with each other through the via 9.

(43) In this step, a transparent conductive film is formed on the substrate 1 with completion of step S5), and then a pattern comprising the pixel electrode layer 8 is formed on the passivation layer 7 by one patterning process using a mask, and the drain layer 3 and the pixel electrode layer 8 are connected through the via 9. Here, the transparent conductive film is formed by deposition, sputtering or thermal evaporation. Of course, other masks that can realize this structure may be used.

(44) In the present embodiment, the active layer of the thin film transistor is formed of metal oxide semiconductor, such as at least one material of indium gallium zinc oxide (IGZO), indium zinc oxide, indium tin oxide, or indium gallium tin oxide, such that the electron mobility between the source layer and the drain layer is increased, therefore better electron mobility between the source layer and the drain layer is achieved.

(45) The present embodiment further provides a display device comprising the above-mentioned array substrate. As illustrated in FIG. 4, a plurality of TFTs are disposed as an array on the array substrate.

Embodiment 2

(46) The present embodiment is different from Embodiment 1 in that the active layer in both the thin film transistor and corresponding array substrate in the present embodiment is formed of non-crystalline silicon material.

(47) In this embodiment, the composite layer comprises an active layer and an ohmic contact layer disposed on the active layer. The active layer is formed of non-crystalline silicon material and has a thickness ranging from 200 3000 . The ohmic contact layer is formed of a non-crystalline silicon material doped with phosphor element and has a thickness ranging from 200 3000 .

(48) The manufacturing method of the TFT array substrate in this embodiment is similar with those described in Embodiment 1, except that the step S3) is: forming a pattern comprising the composite layer on the substrate with completion of step S2), the composite layer comprises an active layer and an ohmic contact layer disposed on the active layer (the two layers are deposited respectively during the preparation process). For example, a composite layer is formed on the gate insulating layer and a part of the drain layer by one patterning process using a mask.

(49) In this embodiment, the active layer is formed of non-crystalline silicon material, therefore the electron mobility between the source layer and the drain layer is smaller than the electron mobility in Embodiment 1.

(50) In the thin film transistor and corresponding array substrate in Embodiments 1 and 2, by forming the source and the drain on different layers respectively (specifically, the drain layer and the gate layer are made in the same layer, and the source layer and the data line are made in the same layer), the step of forming a channel between the source layer and the drain layer by etching will not be needed in the manufacturing methods of thin film transistor and array substrate, thereby totally avoiding bridge connection of source and drain, reducing bright spots caused by poor pixels due to process problem and improving yield of the products.

(51) What are described above is related to the illustrative embodiments of the disclosure only and not limitative to the scope of the disclosure; the scopes of the disclosure are defined by the accompanying claims.